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authorJoel Stanley2022-06-23 18:35:28 +0930
committerTom Rini2022-07-06 14:31:29 -0400
commitdedf8e31861d930927f270b9f5d01013fc54466c (patch)
tree05bfb0e6c6ac43cf3fd849e74e86b4a7e90b3c7b /arch
parentf760403f83c40dac72599e22aa6b5f2884a43763 (diff)
ARM: dts: ast2600: Update SDHCI nodes
Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/ast2600-evb.dts24
-rw-r--r--arch/arm/dts/ast2600.dtsi57
2 files changed, 35 insertions, 46 deletions
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index bb438d57cb6..a9bba968160 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -15,9 +15,9 @@
};
aliases {
- mmc0 = &emmc_slot0;
- mmc1 = &sdhci_slot0;
- mmc2 = &sdhci_slot1;
+ mmc0 = &emmc;
+ mmc1 = &sdhci0;
+ mmc2 = &sdhci1;
spi0 = &fmc;
spi1 = &spi1;
spi2 = &spi2;
@@ -134,18 +134,16 @@
};
};
-&emmc {
- u-boot,dm-pre-reloc;
- timing-phase = <0x700ff>;
+
+&emmc_controller {
+ status = "okay";
};
-&emmc_slot0 {
- u-boot,dm-pre-reloc;
- status = "okay";
- bus-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_emmc_default>;
- sdhci-drive-type = <1>;
+&emmc {
+ non-removable;
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ clk-phase-mmc-hs200 = <9>, <225>;
};
&i2c4 {
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index a37d062bcad..ac8cd4d67d8 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -416,60 +416,51 @@
status = "disabled";
};
- sdhci: sdhci@1e740000 {
- #interrupt-cells = <1>;
- compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
- reg = <0x1e740000 0x1000>;
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
- <&scu ASPEED_CLK_GATE_SDEXTCLK>;
- clock-names = "ctrlclk", "extclk";
+ sdc: sdc@1e740000 {
+ compatible = "aspeed,ast2600-sd-controller";
+ reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x1e740000 0x1000>;
+ ranges = <0 0x1e740000 0x10000>;
+ clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
+ status = "disabled";
- sdhci_slot0: sdhci_slot0@100 {
- compatible = "aspeed,sdhci-ast2600";
+ sdhci0: sdhci@1e740100 {
+ compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x100 0x100>;
- interrupts = <0>;
- interrupt-parent = <&sdhci>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
- sdhci_slot1: sdhci_slot1@200 {
- compatible = "aspeed,sdhci-ast2600";
+ sdhci1: sdhci@1e740200 {
+ compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x200 0x100>;
- interrupts = <1>;
- interrupt-parent = <&sdhci>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
- emmc: emmc@1e750000 {
- #interrupt-cells = <1>;
- compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
- reg = <0x1e750000 0x1000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
- <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
- clock-names = "ctrlclk", "extclk";
+ emmc_controller: sdc@1e750000 {
+ compatible = "aspeed,ast2600-sd-controller";
+ reg = <0x1e750000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x1e750000 0x1000>;
+ ranges = <0 0x1e750000 0x10000>;
+ clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>;
+ status = "disabled";
- emmc_slot0: emmc_slot0@100 {
- compatible = "aspeed,emmc-ast2600";
+ emmc: sdhci@1e750100 {
+ compatible = "aspeed,ast2600-sdhci";
reg = <0x100 0x100>;
- interrupts = <0>;
- interrupt-parent = <&emmc>;
+ sdhci,auto-cmd12;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_EMMC>;
- status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_default>;
};
};