ram: rockchip: Add rv1126 ddr driver support

Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

5 files changed, 1189 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-rockchip/dram_spec_timing.h b/arch/arm/include/asm/arch-rockchip/dram_spec_timing.h
new file mode 100644
index 00000000000..a691e97a8b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/dram_spec_timing.h
@@ -0,0 +1,452 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ROCKCHIP_DRAM_SPEC_TIMING_H__
+#define __ROCKCHIP_DRAM_SPEC_TIMING_H__
+
+enum ddr3_speed_rate {
+	/* 5-5-5 */
+	DDR3_800D = 0,
+	/* 6-6-6 */
+	DDR3_800E = 1,
+	/* 6-6-6 */
+	DDR3_1066E = 2,
+	/* 7-7-7 */
+	DDR3_1066F = 3,
+	/* 8-8-8 */
+	DDR3_1066G = 4,
+	/* 7-7-7 */
+	DDR3_1333F = 5,
+	/* 8-8-8 */
+	DDR3_1333G = 6,
+	/* 9-9-9 */
+	DDR3_1333H = 7,
+	/* 10-10-10 */
+	DDR3_1333J = 8,
+	/* 8-8-8 */
+	DDR3_1600G = 9,
+	/* 9-9-9 */
+	DDR3_1600H = 10,
+	/* 10-10-10 */
+	DDR3_1600J = 11,
+	/* 11-11-11 */
+	DDR3_1600K = 12,
+	/* 10-10-10 */
+	DDR3_1866J = 13,
+	/* 11-11-11 */
+	DDR3_1866K = 14,
+	/* 12-12-12 */
+	DDR3_1866L = 15,
+	/* 13-13-13 */
+	DDR3_1866M = 16,
+	/* 11-11-11 */
+	DDR3_2133K = 17,
+	/* 12-12-12 */
+	DDR3_2133L = 18,
+	/* 13-13-13 */
+	DDR3_2133M = 19,
+	/* 14-14-14 */
+	DDR3_2133N = 20,
+	DDR3_DEFAULT = 21,
+};
+
+enum ddr4_speed_rate {
+	/* DDR4_1600J (10-10-10) */
+	DDR4_1600J = 0,
+	/* DDR4_1600K (11-11-11) */
+	DDR4_1600K = 1,
+	/* DDR4_1600L (12-12-12) */
+	DDR4_1600L = 2,
+	/* DDR4_1800L (12-12-12) */
+	DDR4_1866L = 3,
+	/* DDR4_1800M (13-13-13) */
+	DDR4_1866M = 4,
+	/* DDR4_1800N (14-14-14) */
+	DDR4_1866N = 5,
+	/* DDR4_2133N (14-14-14) */
+	DDR4_2133N = 6,
+	/* DDR4_2133P (15-15-15) */
+	DDR4_2133P = 7,
+	/* DDR4_2133R (16-16-16) */
+	DDR4_2133R = 8,
+	/* DDR4_2400P (15-15-15) */
+	DDR4_2400P = 9,
+	/* DDR4_2400R (16-16-16) */
+	DDR4_2400R = 10,
+	/* DDR4_2400U (18-18-18) */
+	DDR4_2400U = 11,
+	/* DEFAULT */
+	DDR4_DEFAULT = 12,
+};
+
+/* mr0 for ddr3 */
+#define DDR3_BL8		(0)
+#define DDR3_BC4_8		(1)
+#define DDR3_BC4		(2)
+#define DDR3_CL(n)		(((((n) - 4) & 0x7) << 4)\
+				| ((((n) - 4) & 0x8) >> 1))
+#define DDR3_WR(n)		(((n) & 0x7) << 9)
+#define DDR3_DLL_RESET		(1 << 8)
+#define DDR3_DLL_DERESET	(0 << 8)
+
+/* mr1 for ddr3 */
+#define DDR3_DLL_ENABLE		(0)
+#define DDR3_DLL_DISABLE	(1)
+#define DDR3_MR1_AL(n)		(((n) & 0x3) << 3)
+
+#define DDR3_DS_40		(0)
+#define DDR3_DS_34		BIT(1)
+#define DDR3_DS_MASK		((1 << 1) | (1 << 5))
+#define DDR3_RTT_NOM_MASK	((1 << 2) | (1 << 6) | (1 << 9))
+#define DDR3_RTT_NOM_DIS	(0)
+#define DDR3_RTT_NOM_60		BIT(2)
+#define DDR3_RTT_NOM_120	BIT(6)
+#define DDR3_RTT_NOM_40		((1 << 2) | (1 << 6))
+#define DDR3_TDQS		BIT(11)
+
+/* mr2 for ddr3 */
+#define DDR3_MR2_CWL(n)		((((n) - 5) & 0x7) << 3)
+#define DDR3_RTT_WR_DIS		(0)
+#define DDR3_RTT_WR_60		(1 << 9)
+#define DDR3_RTT_WR_120		(2 << 9)
+
+/*
+ * MR0 (Device Information)
+ * 0:DAI complete, 1:DAI still in progress
+ */
+#define LPDDR2_DAI		(0x1)
+/* 0:S2 or S4 SDRAM, 1:NVM */
+#define LPDDR2_DI		(0x1 << 1)
+/* 0:DNV not supported, 1:DNV supported */
+#define LPDDR2_DNVI		(0x1 << 2)
+#define LPDDR2_RZQI		(0x3 << 3)
+
+/*
+ * 00:RZQ self test not supported,
+ * 01:ZQ-pin may connect to VDDCA or float
+ * 10:ZQ-pin may short to GND.
+ * 11:ZQ-pin self test completed, no error condition detected.
+ */
+
+/* MR1 (Device Feature) */
+#define LPDDR2_BL4		(0x2)
+#define LPDDR2_BL8		(0x3)
+#define LPDDR2_BL16		(0x4)
+#define LPDDR2_N_WR(n)		(((n) - 2) << 5)
+
+/* MR2 (Device Feature 2) */
+#define LPDDR2_RL3_WL1		(0x1)
+#define LPDDR2_RL4_WL2		(0x2)
+#define LPDDR2_RL5_WL2		(0x3)
+#define LPDDR2_RL6_WL3		(0x4)
+#define LPDDR2_RL7_WL4		(0x5)
+#define LPDDR2_RL8_WL4		(0x6)
+
+/* MR3 (IO Configuration 1) */
+#define LPDDR2_DS_34		(0x1)
+#define LPDDR2_DS_40		(0x2)
+#define LPDDR2_DS_48		(0x3)
+#define LPDDR2_DS_60		(0x4)
+#define LPDDR2_DS_80		(0x6)
+/* optional */
+#define LPDDR2_DS_120		(0x7)
+
+/* MR4 (Device Temperature) */
+#define LPDDR2_TREF_MASK	(0x7)
+#define LPDDR2_4_TREF		(0x1)
+#define LPDDR2_2_TREF		(0x2)
+#define LPDDR2_1_TREF		(0x3)
+#define LPDDR2_025_TREF		(0x5)
+#define LPDDR2_025_TREF_DERATE	(0x6)
+
+#define LPDDR2_TUF		(0x1 << 7)
+
+/* MR8 (Basic configuration 4) */
+#define LPDDR2_S4		(0x0)
+#define LPDDR2_S2		(0x1)
+#define LPDDR2_N		(0x2)
+/* Unit:MB */
+#define LPDDR2_DENSITY(mr8)	(8 << (((mr8) >> 2) & 0xf))
+#define LPDDR2_IO_WIDTH(mr8)	(32 >> (((mr8) >> 6) & 0x3))
+
+/* MR10 (Calibration) */
+#define LPDDR2_ZQINIT		(0xff)
+#define LPDDR2_ZQCL		(0xab)
+#define LPDDR2_ZQCS		(0x56)
+#define LPDDR2_ZQRESET		(0xc3)
+
+/* MR16 (PASR Bank Mask), S2 SDRAM Only */
+#define LPDDR2_PASR_FULL	(0x0)
+#define LPDDR2_PASR_1_2		(0x1)
+#define LPDDR2_PASR_1_4		(0x2)
+#define LPDDR2_PASR_1_8		(0x3)
+
+/*
+ * MR0 (Device Information)
+ * 0:DAI complete,
+ * 1:DAI still in progress
+ */
+#define LPDDR3_DAI		(0x1)
+/*
+ * 00:RZQ self test not supported,
+ * 01:ZQ-pin may connect to VDDCA or float
+ * 10:ZQ-pin may short to GND.
+ * 11:ZQ-pin self test completed, no error condition detected.
+ */
+#define LPDDR3_RZQI		(0x3 << 3)
+/*
+ * 0:DRAM does not support WL(Set B),
+ * 1:DRAM support WL(Set B)
+ */
+#define LPDDR3_WL_SUPOT		BIT(6)
+/*
+ * 0:DRAM does not support RL=3,nWR=3,WL=1;
+ * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
+ */
+#define LPDDR3_RL3_SUPOT	BIT(7)
+
+/* MR1 (Device Feature) */
+#define LPDDR3_BL8		(0x3)
+#define LPDDR3_N_WR(n)		((n) << 5)
+
+/* MR2 (Device Feature 2), WL Set A,default */
+/* <=166MHz,optional*/
+#define LPDDR3_RL3_WL1		(0x1)
+/* <=400MHz*/
+#define LPDDR3_RL6_WL3		(0x4)
+/* <=533MHz*/
+#define LPDDR3_RL8_WL4		(0x6)
+/* <=600MHz*/
+#define LPDDR3_RL9_WL5		(0x7)
+/* <=667MHz,default*/
+#define LPDDR3_RL10_WL6		(0x8)
+/* <=733MHz*/
+#define LPDDR3_RL11_WL6		(0x9)
+/* <=800MHz*/
+#define LPDDR3_RL12_WL6		(0xa)
+/* <=933MHz*/
+#define LPDDR3_RL14_WL8		(0xc)
+/* <=1066MHz*/
+#define LPDDR3_RL16_WL8		(0xe)
+
+/* WL Set B, optional */
+/* <=667MHz,default*/
+#define LPDDR3_RL10_WL8		(0x8)
+/* <=733MHz*/
+#define LPDDR3_RL11_WL9		(0x9)
+/* <=800MHz*/
+#define LPDDR3_RL12_WL9		(0xa)
+/* <=933MHz*/
+#define LPDDR3_RL14_WL11	(0xc)
+/* <=1066MHz*/
+#define LPDDR3_RL16_WL13	(0xe)
+
+/* 1:enable nWR programming > 9(default)*/
+#define LPDDR3_N_WRE		BIT(4)
+/* 1:Select WL Set B*/
+#define LPDDR3_WL_S		BIT(6)
+/* 1:enable*/
+#define LPDDR3_WR_LEVEL		BIT(7)
+
+/* MR3 (IO Configuration 1) */
+#define LPDDR3_DS_34		(0x1)
+#define LPDDR3_DS_40		(0x2)
+#define LPDDR3_DS_48		(0x3)
+#define LPDDR3_DS_60		(0x4)
+#define LPDDR3_DS_80		(0x6)
+#define LPDDR3_DS_34D_40U	(0x9)
+#define LPDDR3_DS_40D_48U	(0xa)
+#define LPDDR3_DS_34D_48U	(0xb)
+
+/* MR4 (Device Temperature) */
+#define LPDDR3_TREF_MASK	(0x7)
+/* SDRAM Low temperature operating limit exceeded */
+#define LPDDR3_LT_EXED		(0x0)
+#define LPDDR3_4_TREF		(0x1)
+#define LPDDR3_2_TREF		(0x2)
+#define LPDDR3_1_TREF		(0x3)
+#define LPDDR3_05_TREF		(0x4)
+#define LPDDR3_025_TREF		(0x5)
+#define LPDDR3_025_TREF_DERATE	(0x6)
+/* SDRAM High temperature operating limit exceeded */
+#define LPDDR3_HT_EXED		(0x7)
+
+/* 1:value has changed since last read of MR4 */
+#define LPDDR3_TUF		(0x1 << 7)
+
+/* MR8 (Basic configuration 4) */
+#define LPDDR3_S8		(0x3)
+#define LPDDR3_DENSITY(mr8)	(8 << (((mr8) >> 2) & 0xf))
+#define LPDDR3_IO_WIDTH(mr8)	(32 >> (((mr8) >> 6) & 0x3))
+
+/* MR10 (Calibration) */
+#define LPDDR3_ZQINIT		(0xff)
+#define LPDDR3_ZQCL		(0xab)
+#define LPDDR3_ZQCS		(0x56)
+#define LPDDR3_ZQRESET		(0xc3)
+
+/* MR11 (ODT Control) */
+#define LPDDR3_ODT_60		(1)
+#define LPDDR3_ODT_120		(2)
+#define LPDDR3_ODT_240		(3)
+#define LPDDR3_ODT_DIS		(0)
+
+/* MR2 (Device Feature 2) */
+/* RL & nRTP for DBI-RD Disabled */
+#define LPDDR4_RL6_NRTP8	(0x0)
+#define LPDDR4_RL10_NRTP8	(0x1)
+#define LPDDR4_RL14_NRTP8	(0x2)
+#define LPDDR4_RL20_NRTP8	(0x3)
+#define LPDDR4_RL24_NRTP10	(0x4)
+#define LPDDR4_RL28_NRTP12	(0x5)
+#define LPDDR4_RL32_NRTP14	(0x6)
+#define LPDDR4_RL36_NRTP16	(0x7)
+/* RL & nRTP for DBI-RD Disabled */
+#define LPDDR4_RL12_NRTP8	(0x1)
+#define LPDDR4_RL16_NRTP8	(0x2)
+#define LPDDR4_RL22_NRTP8	(0x3)
+#define LPDDR4_RL28_NRTP10	(0x4)
+#define LPDDR4_RL32_NRTP12	(0x5)
+#define LPDDR4_RL36_NRTP14	(0x6)
+#define LPDDR4_RL40_NRTP16	(0x7)
+/* WL Set A,default */
+#define LPDDR4_A_WL4		(0x0 << 3)
+#define LPDDR4_A_WL6		(0x1 << 3)
+#define LPDDR4_A_WL8		(0x2 << 3)
+#define LPDDR4_A_WL10		(0x3 << 3)
+#define LPDDR4_A_WL12		(0x4 << 3)
+#define LPDDR4_A_WL14		(0x5 << 3)
+#define LPDDR4_A_WL16		(0x6 << 3)
+#define LPDDR4_A_WL18		(0x7 << 3)
+/* WL Set B, optional */
+#define LPDDR4_B_WL4		(0x0 << 3)
+#define LPDDR4_B_WL8		(0x1 << 3)
+#define LPDDR4_B_WL12		(0x2 << 3)
+#define LPDDR4_B_WL18		(0x3 << 3)
+#define LPDDR4_B_WL22		(0x4 << 3)
+#define LPDDR4_B_WL26		(0x5 << 3)
+#define LPDDR4_B_WL30		(0x6 << 3)
+#define LPDDR4_B_WL34		(0x7 << 3)
+/* 1:Select WL Set B*/
+#define LPDDR4_WL_B		BIT(6)
+/* 1:enable*/
+#define LPDDR4_WR_LEVEL		BIT(7)
+
+/* MR3 */
+#define LPDDR4_VDDQ_2_5		(0)
+#define LPDDR4_VDDQ_3		(1)
+#define LPDDR4_PU_CAL_MASK	(1)
+#define LPDDR4_WRPST_0_5_TCK	(0 << 1)
+#define LPDDR4_WRPST_1_5_TCK	(1 << 1)
+#define LPDDR4_PPR_EN		(1 << 2)
+/* PDDS */
+#define LPDDR4_PDDS_MASK	(0x7 << 3)
+#define LPDDR4_PDDS_SHIFT	(3)
+#define LPDDR4_PDDS_240		(0x1 << 3)
+#define LPDDR4_PDDS_120		(0x2 << 3)
+#define LPDDR4_PDDS_80		(0x3 << 3)
+#define LPDDR4_PDDS_60		(0x4 << 3)
+#define LPDDR4_PDDS_48		(0x5 << 3)
+#define LPDDR4_PDDS_40		(0x6 << 3)
+#define LPDDR4_DBI_RD_EN	BIT(6)
+#define LPDDR4_DBI_WR_EN	BIT(7)
+
+/* MR11 (ODT Control) */
+#define LPDDR4_DQODT_MASK	(0x7)
+#define LPDDR4_DQODT_SHIFT	(0x0)
+#define LPDDR4_DQODT_240	(1)
+#define LPDDR4_DQODT_120	(2)
+#define LPDDR4_DQODT_80		(3)
+#define LPDDR4_DQODT_60		(4)
+#define LPDDR4_DQODT_48		(5)
+#define LPDDR4_DQODT_40		(6)
+#define LPDDR4_DQODT_DIS	(0)
+#define LPDDR4_CAODT_MASK	(0x7 << 4)
+#define LPDDR4_CAODT_SHIFT	(4)
+#define LPDDR4_CAODT_240	(1 << 4)
+#define LPDDR4_CAODT_120	(2 << 4)
+#define LPDDR4_CAODT_80		(3 << 4)
+#define LPDDR4_CAODT_60		(4 << 4)
+#define LPDDR4_CAODT_48		(5 << 4)
+#define LPDDR4_CAODT_40		(6 << 4)
+#define LPDDR4_CAODT_DIS	(0 << 4)
+
+/* MR22 */
+#define LPDDR4_ODTE_CK_SHIFT	(3)
+#define LPDDR4_ODTE_CS_SHIFT	(4)
+#define LPDDR4_ODTD_CA_SHIFT	(5)
+#define LPDDR4_SOC_ODT_MASK	(0x7)
+#define LPDDR4_SOC_ODT_SHIFT	(0)
+#define LPDDR4_SOC_ODT_240	(1)
+#define LPDDR4_SOC_ODT_120	(2)
+#define LPDDR4_SOC_ODT_80	(3)
+#define LPDDR4_SOC_ODT_60	(4)
+#define LPDDR4_SOC_ODT_48	(5)
+#define LPDDR4_SOC_ODT_40	(6)
+#define LPDDR4_SOC_ODT_DIS	(0)
+
+/* LPDDR4x */
+/* MR3 */
+#define LPDDR4X_VDDQ_0_6	(0)
+#define LPDDR4X_VDDQ_0_5	(1)
+
+/* mr0 for ddr4 */
+#define DDR4_BL8		(0)
+#define DDR4_BC4_8		(1)
+#define DDR4_BC4		(2)
+#define DDR4_WR_RTP(n)		((n) << 9)
+#define DDR4_CL(n)		((((n) & 0xe) << 3) | ((n) & 1) << 2)
+#define DDR4_DLL_RESET(n)	((n) << 8)
+#define DDR4_DLL_ON		BIT(0)
+#define DDR4_DLL_OFF		(0 << 0)
+
+/* mr1 for ddr4 */
+#define DDR4_AL			((n) << 3)
+#define DDR4_DS_34		(0)
+#define DDR4_DS_48		BIT(1)
+#define DDR4_DS_MASK		(0x3 << 1)
+#define DDR4_RTT_NOM_MASK	(0x7 << 8)
+#define DDR4_RTT_NOM_DIS	(0)
+#define DDR4_RTT_NOM_60		BIT(8)
+#define DDR4_RTT_NOM_120	(2 << 8)
+#define DDR4_RTT_NOM_40		(0x3 << 8)
+#define DDR4_RTT_NOM_240	(0x4 << 8)
+#define DDR4_RTT_NOM_48		(0x5 << 8)
+#define DDR4_RTT_NOM_80		(0x6 << 8)
+#define DDR4_RTT_NOM_34		(0x7 << 8)
+
+/* mr2 for ddr4 */
+#define DDR4_MR2_CWL(n)		((n) << 3)
+#define DDR4_RTT_WR_DIS		(0)
+#define DDR4_RTT_WR_120		BIT(9)
+#define DDR4_RTT_WR_240		(2 << 9)
+
+/* mr4 for ddr4 */
+#define DDR4_READ_PREAMBLE(n)	((n) << 11)
+#define DDR4_WRITE_PREAMBLE(n)	((n) << 12)
+#define DDR4_READ_PREAMBLE_TRAIN(n)	((n) << 10)
+
+/* mr5 for ddr4 */
+#define DDR4_RD_DBI(n)		((n) << 12)
+#define DDR4_WR_DBI(n)		((n) << 11)
+#define DDR4_DM(n)		((n) << 10)
+#define DDR4_RTT_PARK_DIS	(0 << 6)
+#define DDR4_RTT_PARK_60	(1 << 6)
+#define DDR4_RTT_PARK_120	(2 << 6)
+#define DDR4_RTT_PARK_40	(3 << 6)
+#define DDR4_RTT_PARK_240	(4 << 6)
+#define DDR4_RTT_PARK_48	(5 << 6)
+#define DDR4_RTT_PARK_80	(6 << 6)
+#define DDR4_RTT_PARK_34	(7 << 6)
+#define DIS_ODT_PD		(1 << 5)
+#define EN_ODT_PD		(0 << 5)
+
+/* mr6 for ddr4 */
+#define DDR4_TCCD_L(n)		(((n) - 4) << 10)
+
+#define PS_2_CLK(freq, ps)	(((uint64_t)(ps) / 100 * (uint64_t)(freq) +\
+				9999) / 10000)
+
+#endif /* __ROCKCHIP_DRAM_SPEC_TIMING_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index a14b37cbc5c..e53e5a9ca58 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -15,6 +15,210 @@
 #define MIN(a, b)	(((a) > (b)) ? (b) : (a))
 #define MAX(a, b)	(((a) > (b)) ? (a) : (b))
 
+/* get head info for initial */
+#define DDR_FREQ_F0_SHIFT		(0)
+#define DDR_FREQ_F1_SHIFT		(12)
+#define DDR_FREQ_F2_SHIFT		(0)
+#define DDR_FREQ_F3_SHIFT		(12)
+#define DDR_FREQ_F4_SHIFT		(0)
+#define DDR_FREQ_F5_SHIFT		(12)
+#define DDR_FREQ_MASK			(0xfff)
+
+#define UART_INFO_ID_SHIFT		(28)
+#define UART_INFO_IOMUX_SHIFT		(24)
+#define UART_INFO_BAUD_SHIFT		(0)
+#define UART_INFO_ID(n)			(((n) >> 28) & 0xf)
+#define UART_INFO_IOMUX(n)		(((n) >> 24) & 0xf)
+#define UART_INFO_BAUD(n)		((n) & 0xffffff)
+
+/* g_ch_info[15:0]: g_stdby_idle */
+#define STANDBY_IDLE(n)			((n) & 0xffff)
+
+#define SR_INFO(n)			(((n) >> 16) & 0xffff)
+#define PD_INFO(n)			((n) & 0xffff)
+
+#define FIRST_SCAN_CH(n)		(((n) >> 28) & 0xf)
+#define CHANNEL_MASK(n)			(((n) >> 24) & 0xf)
+#define STRIDE_TYPE(n)			(((n) >> 16) & 0xff)
+
+#define DDR_2T_INFO(n)			((n) & 1)
+#define PLL_SSMOD_SPREAD(n)		(((n) >> 1) & 0xff)
+#define PLL_SSMOD_DIV(n)		(((n) >> 9) & 0xff)
+#define PLL_SSMOD_DOWNSPREAD(n)		(((n) >> 17) & 0x3)
+
+/* sdram_head_info_v2 define */
+/* for *_drv_odten and *_drv_odtoff */
+#define PHY_DQ_DRV_SHIFT		0
+#define PHY_CA_DRV_SHIFT		8
+#define PHY_CLK_DRV_SHIFT		16
+#define DRAM_DQ_DRV_SHIFT		24
+#define DRV_INFO_PHY_DQ_DRV(n)		((n) & 0xff)
+#define DRV_INFO_PHY_CA_DRV(n)		(((n) >> PHY_CA_DRV_SHIFT) & 0xff)
+#define DRV_INFO_PHY_CLK_DRV(n)		(((n) >> PHY_CLK_DRV_SHIFT) & 0xff)
+#define DRV_INFO_DRAM_DQ_DRV(n)		(((n) >> DRAM_DQ_DRV_SHIFT) & 0xff)
+
+/* for *_odt_info */
+#define DRAM_ODT_SHIFT			0
+#define PHY_ODT_SHIFT			8
+#define PHY_ODT_PUUP_EN_SHIFT		18
+#define PHY_ODT_PUDN_EN_SHIFT		19
+#define ODT_INFO_DRAM_ODT(n)		(((n) >> DRAM_ODT_SHIFT) & 0xff)
+#define ODT_INFO_PHY_ODT(n)		(((n) >> PHY_ODT_SHIFT) & 0x3ff)
+#define ODT_INFO_PULLUP_EN(n)		(((n) >> PHY_ODT_PUUP_EN_SHIFT) & 1)
+#define ODT_INFO_PULLDOWN_EN(n)		(((n) >> PHY_ODT_PUDN_EN_SHIFT) & 1)
+
+/* for *odt_en_freq; */
+#define DRAM_ODT_EN_FREQ_SHIFT		0
+#define PHY_ODT_EN_FREQ_SHIFT		12
+#define DRAMODT_EN_FREQ(n)		(((n) >> DRAM_ODT_EN_FREQ_SHIFT) & \
+					 0xfff)
+#define PHYODT_EN_FREQ(n)		(((n) >> PHY_ODT_EN_FREQ_SHIFT) & 0xfff)
+
+#define PHY_DQ_SR_SHIFT			0
+#define PHY_CA_SR_SHIFT			8
+#define PHY_CLK_SR_SHIFT		16
+#define DQ_SR_INFO(n)			(((n) >> PHY_DQ_SR_SHIFT) & 0xff)
+#define CA_SR_INFO(n)			(((n) >> PHY_CA_SR_SHIFT) & 0xff)
+#define CLK_SR_INFO(n)			(((n) >> PHY_CLK_SR_SHIFT) & 0xff)
+
+/* LP4 */
+#define LP4_CA_ODT_SHIFT			(18)
+#define LP4_DRV_PU_CAL_ODTEN_SHIFT		(26)
+#define LP4_DRV_PU_CAL_ODTOFF_SHIFT		(27)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT	(28)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT	(29)
+#define ODT_INFO_LP4_CA_ODT(n)			(((n) >> LP4_CA_ODT_SHIFT) & \
+						 0xff)
+#define LP4_DRV_PU_CAL_ODTEN(n)		\
+	(((n) >> LP4_DRV_PU_CAL_ODTEN_SHIFT) & 1)
+#define LP4_DRV_PU_CAL_ODTOFF(n)	\
+	(((n) >> LP4_DRV_PU_CAL_ODTOFF_SHIFT) & 1)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN(n)	\
+	(((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) & 1)
+#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(n)	\
+	(((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT) & 1)
+
+#define PHY_LP4_CS_DRV_ODTEN_SHIFT	(0)
+#define PHY_LP4_CS_DRV_ODTOFF_SHIFT	(8)
+#define LP4_ODTE_CK_SHIFT		(16)
+#define LP4_ODTE_CS_EN_SHIFT		(17)
+#define LP4_ODTD_CA_EN_SHIFT		(18)
+#define PHY_LP4_CS_DRV_ODTEN(n)		\
+	(((n) >> PHY_LP4_CS_DRV_ODTEN_SHIFT) & 0xff)
+#define PHY_LP4_CS_DRV_ODTOFF(n)	\
+	(((n) >> PHY_LP4_CS_DRV_ODTOFF_SHIFT) & 0xff)
+#define LP4_ODTE_CK_EN(n)		(((n) >> LP4_ODTE_CK_SHIFT) & 1)
+#define LP4_ODTE_CS_EN(n)		(((n) >> LP4_ODTE_CS_EN_SHIFT) & 1)
+#define LP4_ODTD_CA_EN(n)		(((n) >> LP4_ODTD_CA_EN_SHIFT) & 1)
+
+#define PHY_LP4_DQ_VREF_SHIFT		(0)
+#define LP4_DQ_VREF_SHIFT		(10)
+#define LP4_CA_VREF_SHIFT		(20)
+
+#define PHY_LP4_DQ_VREF(n)		\
+	(((n) >> PHY_LP4_DQ_VREF_SHIFT) & 0x3ff)
+#define LP4_DQ_VREF(n)			(((n) >> LP4_DQ_VREF_SHIFT) & 0x3ff)
+#define LP4_CA_VREF(n)			(((n) >> LP4_CA_VREF_SHIFT) & 0x3ff)
+
+#define LP4_DQ_ODT_EN_FREQ_SHIFT	(0)
+#define PHY_LP4_ODT_EN_FREQ_SHIFT	(12)
+#define LP4_CA_ODT_EN_FREQ_SHIFT	(0)
+#define PHY_LP4_ODT_EN_FREQ(n)		\
+	(((n) >> PHY_LP4_ODT_EN_FREQ_SHIFT) & 0xfff)
+#define LP4_DQ_ODT_EN_FREQ(n)		\
+	(((n) >> LP4_DQ_ODT_EN_FREQ_SHIFT) & 0xfff)
+#define LP4_CA_ODT_EN_FREQ(n)		\
+	(((n) >> LP4_CA_ODT_EN_FREQ_SHIFT) & 0xfff)
+
+struct sdram_head_info_v0 {
+	u32 start_tag;
+	u32 version_info;
+	u32 gcpu_gen_freq;
+	u32 g_d2_lp2_freq;
+	u32 g_d3_lp3_freq;
+	u32 g_d4_lp4_freq;
+	u32 g_uart_info;
+	u32 g_sr_pd_idle;
+	u32 g_ch_info;
+	u32 g_2t_info;
+	u32 reserved11;
+	u32 reserved12;
+	u32 reserved13;
+};
+
+struct index_info {
+	u8 offset;
+	u8 size;
+};
+
+struct sdram_head_info_index_v2 {
+	u32 start_tag;
+	u32 version_info;
+	struct index_info cpu_gen_index;
+	struct index_info global_index;
+
+	struct index_info ddr2_index;
+	struct index_info ddr3_index;
+
+	struct index_info ddr4_index;
+	struct index_info ddr5_index;
+
+	struct index_info lp2_index;
+	struct index_info lp3_index;
+
+	struct index_info lp4_index;
+	struct index_info lp5_index;
+
+	struct index_info skew_index;
+	struct index_info dq_map_index;
+
+	struct index_info lp4x_index;
+	struct index_info reserved;
+};
+
+struct global_info {
+	u32 uart_info;
+	u32 sr_pd_info;
+	u32 ch_info;
+	u32 info_2t;
+	u32 reserved[4];
+};
+
+struct ddr2_3_4_lp2_3_info {
+	u32 ddr_freq0_1;
+	u32 ddr_freq2_3;
+	u32 ddr_freq4_5;
+	u32 drv_when_odten;
+	u32 drv_when_odtoff;
+	u32 odt_info;
+	u32 odten_freq;
+	u32 sr_when_odten;
+	u32 sr_when_odtoff;
+};
+
+struct lp4_info {
+	u32 ddr_freq0_1;
+	u32 ddr_freq2_3;
+	u32 ddr_freq4_5;
+	u32 drv_when_odten;
+	u32 drv_when_odtoff;
+	u32 odt_info;
+	u32 dq_odten_freq;
+	u32 sr_when_odten;
+	u32 sr_when_odtoff;
+	u32 ca_odten_freq;
+	u32 cs_drv_ca_odt_info;
+	u32 vref_when_odten;
+	u32 vref_when_odtoff;
+};
+
+struct dq_map_info {
+	u32 byte_map[2];
+	u32 lp3_dq0_7_map;
+	u32 lp2_dq0_7_map;
+	u32 ddr4_dq_map[4];
+};
+
 struct sdram_cap_info {
 	unsigned int rank;
 	/* dram column number, 0 means this channel is invalid */
@@ -46,6 +250,14 @@ struct sdram_base_params {
 };
 
 #define DDR_SYS_REG_VERSION		(0x2)
+/* for modify tRFC and related timing */
+#define DIE_CAP_512MBIT	64
+#define DIE_CAP_1GBIT	128
+#define DIE_CAP_2GBIT	256
+#define DIE_CAP_4GBIT	512
+#define DIE_CAP_8GBIT	1024
+#define DIE_CAP_16GBIT	2048
+#define DIE_CAP_32GBIT	4096
 /*
  * sys_reg2 bitfield struct
  * [31]		row_3_4_ch1
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_msch.h b/arch/arm/include/asm/arch-rockchip/sdram_msch.h
index cfb3d9cc869..d1926f4bf20 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_msch.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_msch.h
@@ -57,6 +57,18 @@ union noc_devtodev0 {
 	} b;
 };
 
+union noc_devtodev_rv1126 {
+	u32 d32;
+	struct {
+		unsigned busrdtord : 3;
+		unsigned reserved0 : 1;
+		unsigned busrdtowr : 4;
+		unsigned buswrtord : 4;
+		unsigned buswrtowr : 3;
+		unsigned reserved2 : 17;
+	} b;
+};
+
 union noc_ddrmode {
 	u32 d32;
 	struct {
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_phy_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_phy_rv1126.h
new file mode 100644
index 00000000000..5b64ec33528
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_phy_rv1126.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK1126_PHY_H
+#define _ASM_ARCH_SDRAM_RK1126_PHY_H
+
+/* PHY_REG0 */
+#define DIGITAL_DERESET			BIT(3)
+#define ANALOG_DERESET			BIT(2)
+#define DIGITAL_RESET			(0 << 3)
+#define ANALOG_RESET			(0 << 2)
+
+/* PHY_REG1 */
+#define PHY_DDR2			(0)
+#define PHY_LPDDR2			(1)
+#define PHY_DDR3			(2)
+#define PHY_LPDDR3			(3)
+#define PHY_DDR4			(4)
+#define PHY_DDR5			(5)
+#define PHY_BL_4			(0 << 3)
+#define PHY_BL_8_OR_16			BIT(3)
+
+/* PHY_REG2 */
+#define PHY_DTT_EN			BIT(0)
+#define PHY_DTT_DISB			(0 << 0)
+#define PHY_WRITE_LEVELING_EN		BIT(2)
+#define PHY_WRITE_LEVELING_DISB		(0 << 2)
+#define PHY_SELECT_CS0			(2)
+#define PHY_SELECT_CS1			(1)
+#define PHY_SELECT_CS0_1		(0)
+#define PHY_WRITE_LEVELING_SELECTCS(n)	((n) << 6)
+#define PHY_DATA_TRAINING_SELECTCS(n)	((n) << 4)
+
+/* PHY_REGf */
+#define PHY_DQ_WIDTH_MASK		(0xf)
+
+/* PHY_REG51 */
+#define PHY_PBDIV_BIT9_MASK		BIT(0)
+#define PHY_PBDIV_BIT9_SHIFT	(0)
+#define PHY_POSTDIV_EN_MASK		BIT(7)
+#define PHY_POSTDIV_EN_SHIFT	(7)
+
+/* PHY_REG52 */
+#define PHY_PREDIV_MASK			(0x1F)
+#define PHY_PREDIV_SHIFT		(0)
+
+/* PHY_REG53*/
+#define PHY_POSTDIV_MASK		(0x7)
+#define PHY_POSTDIV_SHIFT		(5)
+#define PHY_PD_DISB			BIT(3)
+
+/* PHY_REG90 */
+#define PHY_PLL_LOCK			BIT(2)
+
+struct ca_skew {
+	u32 a0_a3_a3_cke1_a_de_skew;
+	u32 a1_ba1_null_cke0_b_de_skew;
+	u32 a2_a9_a9_a4_a_de_skew;
+	u32 a3_a15_null_a5_b_de_skew;
+	u32 a4_a6_a6_ck_a_de_skew;
+	u32 a5_a12_null_odt0_b_de_skew;
+	u32 a6_ba2_null_a0_a_de_skew;
+	u32 a7_a4_a4_odt0_a_de_skew;
+	u32 a8_a1_a1_cke0_a_de_skew;
+	u32 a9_a5_a5_a5_a_de_skew;
+	u32 a10_a8_a8_clkb_a_de_skew;
+	u32 a11_a7_a7_ca2_a_de_skew;
+	u32 a12_rasn_null_ca1_a_de_skew;
+	u32 a13_a13_null_ca3_a_de_skew;
+	u32 a14_a14_null_csb1_b_de_skew;
+	u32 a15_a10_null_ca0_b_de_skew;
+	u32 a16_a11_null_csb0_b_de_skew;
+	u32 a17_null_null_null_de_skew;
+	u32 ba0_csb1_csb1_csb0_a_de_skew;
+	u32 ba1_wen_null_cke1_b_de_skew;
+	u32 bg0_odt1_odt1_csb1_a_de_skew;
+	u32 bg1_a2_a2_odt1_a_de_skew;
+	u32 cke0_casb_null_ca1_b_de_skew;
+	u32 ck_ck_ck_ck_b_de_skew;
+	u32 ckb_ckb_ckb_ckb_b_de_skew;
+	u32 csb0_odt0_odt0_ca2_b_de_skew;
+	u32 odt0_csb0_csb0_ca4_b_de_skew;
+	u32 resetn_resetn_null_resetn_de_skew;
+	u32 actn_cke_cke_ca3_b_de_skew;
+	u32 null_null_null_null_de_skew;
+	u32 csb1_ba0_null_null_de_skew;
+	u32 odt1_a0_a0_odt1_b_de_skew;
+};
+
+#define PHY_REG(base, n)		((base) + 4 * (n))
+#endif /* _ASM_ARCH_SDRAM_RK1126_PHY_H */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
new file mode 100644
index 00000000000..6a07436059c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
@@ -0,0 +1,420 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK1126_H
+#define _ASM_ARCH_SDRAM_RK1126_H
+
+#include <asm/arch-rockchip/dram_spec_timing.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_msch.h>
+#include <asm/arch-rockchip/sdram_pctl_px30.h>
+#include <asm/arch-rockchip/sdram_phy_rv1126.h>
+
+#define AGINGX0_VAL			(4)
+#define AGING_CPU_VAL			(0xff)
+#define AGING_NPU_VAL			(0xff)
+#define AGING_OTHER_VAL			(0x33)
+
+#define PATTERN				(0x5aa5f00f)
+
+#define PHY_DDR3_RON_DISABLE		(0)
+#define PHY_DDR3_RON_455ohm		(1)
+#define PHY_DDR3_RON_230ohm		(2)
+#define PHY_DDR3_RON_153ohm		(3)
+#define PHY_DDR3_RON_115ohm		(4)
+#define PHY_DDR3_RON_91ohm		(5)
+#define PHY_DDR3_RON_76ohm		(6)
+#define PHY_DDR3_RON_65ohm		(7)
+#define PHY_DDR3_RON_57ohm		(16)
+#define PHY_DDR3_RON_51ohm		(17)
+#define PHY_DDR3_RON_46ohm		(18)
+#define PHY_DDR3_RON_41ohm		(19)
+#define PHY_DDR3_RON_38ohm		(20)
+#define PHY_DDR3_RON_35ohm		(21)
+#define PHY_DDR3_RON_32ohm		(22)
+#define PHY_DDR3_RON_30ohm		(23)
+#define PHY_DDR3_RON_28ohm		(24)
+#define PHY_DDR3_RON_27ohm		(25)
+#define PHY_DDR3_RON_25ohm		(26)
+#define PHY_DDR3_RON_24ohm		(27)
+#define PHY_DDR3_RON_23ohm		(28)
+#define PHY_DDR3_RON_22ohm		(29)
+#define PHY_DDR3_RON_21ohm		(30)
+#define PHY_DDR3_RON_20ohm		(31)
+
+#define PHY_DDR3_RTT_DISABLE		(0)
+#define PHY_DDR3_RTT_561ohm		(1)
+#define PHY_DDR3_RTT_282ohm		(2)
+#define PHY_DDR3_RTT_188ohm		(3)
+#define PHY_DDR3_RTT_141ohm		(4)
+#define PHY_DDR3_RTT_113ohm		(5)
+#define PHY_DDR3_RTT_94ohm		(6)
+#define PHY_DDR3_RTT_81ohm		(7)
+#define PHY_DDR3_RTT_72ohm		(16)
+#define PHY_DDR3_RTT_64ohm		(17)
+#define PHY_DDR3_RTT_58ohm		(18)
+#define PHY_DDR3_RTT_52ohm		(19)
+#define PHY_DDR3_RTT_48ohm		(20)
+#define PHY_DDR3_RTT_44ohm		(21)
+#define PHY_DDR3_RTT_41ohm		(22)
+#define PHY_DDR3_RTT_38ohm		(23)
+#define PHY_DDR3_RTT_37ohm		(24)
+#define PHY_DDR3_RTT_34ohm		(25)
+#define PHY_DDR3_RTT_32ohm		(26)
+#define PHY_DDR3_RTT_31ohm		(27)
+#define PHY_DDR3_RTT_29ohm		(28)
+#define PHY_DDR3_RTT_28ohm		(29)
+#define PHY_DDR3_RTT_27ohm		(30)
+#define PHY_DDR3_RTT_25ohm		(31)
+
+#define PHY_DDR4_LPDDR3_RON_DISABLE	(0)
+#define PHY_DDR4_LPDDR3_RON_482ohm	(1)
+#define PHY_DDR4_LPDDR3_RON_244ohm	(2)
+#define PHY_DDR4_LPDDR3_RON_162ohm	(3)
+#define PHY_DDR4_LPDDR3_RON_122ohm	(4)
+#define PHY_DDR4_LPDDR3_RON_97ohm	(5)
+#define PHY_DDR4_LPDDR3_RON_81ohm	(6)
+#define PHY_DDR4_LPDDR3_RON_69ohm	(7)
+#define PHY_DDR4_LPDDR3_RON_61ohm	(16)
+#define PHY_DDR4_LPDDR3_RON_54ohm	(17)
+#define PHY_DDR4_LPDDR3_RON_48ohm	(18)
+#define PHY_DDR4_LPDDR3_RON_44ohm	(19)
+#define PHY_DDR4_LPDDR3_RON_40ohm	(20)
+#define PHY_DDR4_LPDDR3_RON_37ohm	(21)
+#define PHY_DDR4_LPDDR3_RON_34ohm	(22)
+#define PHY_DDR4_LPDDR3_RON_32ohm	(23)
+#define PHY_DDR4_LPDDR3_RON_30ohm	(24)
+#define PHY_DDR4_LPDDR3_RON_28ohm	(25)
+#define PHY_DDR4_LPDDR3_RON_27ohm	(26)
+#define PHY_DDR4_LPDDR3_RON_25ohm	(27)
+#define PHY_DDR4_LPDDR3_RON_24ohm	(28)
+#define PHY_DDR4_LPDDR3_RON_23ohm	(29)
+#define PHY_DDR4_LPDDR3_RON_22ohm	(30)
+#define PHY_DDR4_LPDDR3_RON_21ohm	(31)
+
+#define PHY_DDR4_LPDDR3_RTT_DISABLE	(0)
+#define PHY_DDR4_LPDDR3_RTT_586ohm	(1)
+#define PHY_DDR4_LPDDR3_RTT_294ohm	(2)
+#define PHY_DDR4_LPDDR3_RTT_196ohm	(3)
+#define PHY_DDR4_LPDDR3_RTT_148ohm	(4)
+#define PHY_DDR4_LPDDR3_RTT_118ohm	(5)
+#define PHY_DDR4_LPDDR3_RTT_99ohm	(6)
+#define PHY_DDR4_LPDDR3_RTT_85ohm	(7)
+#define PHY_DDR4_LPDDR3_RTT_76ohm	(16)
+#define PHY_DDR4_LPDDR3_RTT_67ohm	(17)
+#define PHY_DDR4_LPDDR3_RTT_60ohm	(18)
+#define PHY_DDR4_LPDDR3_RTT_55ohm	(19)
+#define PHY_DDR4_LPDDR3_RTT_50ohm	(20)
+#define PHY_DDR4_LPDDR3_RTT_46ohm	(21)
+#define PHY_DDR4_LPDDR3_RTT_43ohm	(22)
+#define PHY_DDR4_LPDDR3_RTT_40ohm	(23)
+#define PHY_DDR4_LPDDR3_RTT_38ohm	(24)
+#define PHY_DDR4_LPDDR3_RTT_36ohm	(25)
+#define PHY_DDR4_LPDDR3_RTT_34ohm	(26)
+#define PHY_DDR4_LPDDR3_RTT_32ohm	(27)
+#define PHY_DDR4_LPDDR3_RTT_31ohm	(28)
+#define PHY_DDR4_LPDDR3_RTT_29ohm	(29)
+#define PHY_DDR4_LPDDR3_RTT_28ohm	(30)
+#define PHY_DDR4_LPDDR3_RTT_27ohm	(31)
+
+#define PHY_LPDDR4_RON_DISABLE		(0)
+#define PHY_LPDDR4_RON_501ohm		(1)
+#define PHY_LPDDR4_RON_253ohm		(2)
+#define PHY_LPDDR4_RON_168ohm		(3)
+#define PHY_LPDDR4_RON_126ohm		(4)
+#define PHY_LPDDR4_RON_101ohm		(5)
+#define PHY_LPDDR4_RON_84ohm		(6)
+#define PHY_LPDDR4_RON_72ohm		(7)
+#define PHY_LPDDR4_RON_63ohm		(16)
+#define PHY_LPDDR4_RON_56ohm		(17)
+#define PHY_LPDDR4_RON_50ohm		(18)
+#define PHY_LPDDR4_RON_46ohm		(19)
+#define PHY_LPDDR4_RON_42ohm		(20)
+#define PHY_LPDDR4_RON_38ohm		(21)
+#define PHY_LPDDR4_RON_36ohm		(22)
+#define PHY_LPDDR4_RON_33ohm		(23)
+#define PHY_LPDDR4_RON_31ohm		(24)
+#define PHY_LPDDR4_RON_29ohm		(25)
+#define PHY_LPDDR4_RON_28ohm		(26)
+#define PHY_LPDDR4_RON_26ohm		(27)
+#define PHY_LPDDR4_RON_25ohm		(28)
+#define PHY_LPDDR4_RON_24ohm		(29)
+#define PHY_LPDDR4_RON_23ohm		(30)
+#define PHY_LPDDR4_RON_22ohm		(31)
+
+#define PHY_LPDDR4_RTT_DISABLE		(0)
+#define PHY_LPDDR4_RTT_604ohm		(1)
+#define PHY_LPDDR4_RTT_303ohm		(2)
+#define PHY_LPDDR4_RTT_202ohm		(3)
+#define PHY_LPDDR4_RTT_152ohm		(4)
+#define PHY_LPDDR4_RTT_122ohm		(5)
+#define PHY_LPDDR4_RTT_101ohm		(6)
+#define PHY_LPDDR4_RTT_87ohm		(7)
+#define PHY_LPDDR4_RTT_78ohm		(16)
+#define PHY_LPDDR4_RTT_69ohm		(17)
+#define PHY_LPDDR4_RTT_62ohm		(18)
+#define PHY_LPDDR4_RTT_56ohm		(19)
+#define PHY_LPDDR4_RTT_52ohm		(20)
+#define PHY_LPDDR4_RTT_48ohm		(21)
+#define PHY_LPDDR4_RTT_44ohm		(22)
+#define PHY_LPDDR4_RTT_41ohm		(23)
+#define PHY_LPDDR4_RTT_39ohm		(24)
+#define PHY_LPDDR4_RTT_37ohm		(25)
+#define PHY_LPDDR4_RTT_35ohm		(26)
+#define PHY_LPDDR4_RTT_33ohm		(27)
+#define PHY_LPDDR4_RTT_32ohm		(28)
+#define PHY_LPDDR4_RTT_30ohm		(29)
+#define PHY_LPDDR4_RTT_29ohm		(30)
+#define PHY_LPDDR4_RTT_27ohm		(31)
+
+#define ADD_CMD_CA			(0x150)
+#define ADD_GROUP_CS0_A			(0x170)
+#define ADD_GROUP_CS0_B			(0x1d0)
+#define ADD_GROUP_CS1_A			(0x1a0)
+#define ADD_GROUP_CS1_B			(0x200)
+
+/* PMUGRF */
+#define PMUGRF_OS_REG0			(0x200)
+#define PMUGRF_OS_REG(n)		(PMUGRF_OS_REG0 + (n) * 4)
+#define PMUGRF_CON_DDRPHY_BUFFEREN_MASK		(0x3 << (12 + 16))
+#define PMUGRF_CON_DDRPHY_BUFFEREN_EN		(0x1 << 12)
+#define PMUGRF_CON_DDRPHY_BUFFEREN_DIS	(0x2 << 12)
+
+/* DDR GRF */
+#define DDR_GRF_CON(n)			(0 + (n) * 4)
+#define DDR_GRF_STATUS_BASE		(0X100)
+#define DDR_GRF_STATUS(n)		(DDR_GRF_STATUS_BASE + (n) * 4)
+#define DDR_GRF_LP_CON			(0x20)
+
+#define SPLIT_MODE_32_L16_VALID		(0)
+#define SPLIT_MODE_32_H16_VALID		(1)
+#define SPLIT_MODE_16_L8_VALID		(2)
+#define SPLIT_MODE_16_H8_VALID		(3)
+
+#define DDR_GRF_SPLIT_CON		(0x10)
+#define SPLIT_MODE_MASK			(0x3)
+#define SPLIT_MODE_OFFSET		(9)
+#define SPLIT_BYPASS_MASK		(1)
+#define SPLIT_BYPASS_OFFSET		(8)
+#define SPLIT_SIZE_MASK			(0xff)
+#define SPLIT_SIZE_OFFSET		(0)
+
+/* SGRF SOC_CON13 */
+#define UPCTL2_ASRSTN_REQ(n)		(((0x1 << 0) << 16) | ((n) << 0))
+#define UPCTL2_PSRSTN_REQ(n)		(((0x1 << 1) << 16) | ((n) << 1))
+#define UPCTL2_SRSTN_REQ(n)		(((0x1 << 2) << 16) | ((n) << 2))
+
+/* CRU define */
+/* CRU_PLL_CON0 */
+#define PB(n)				((0x1 << (15 + 16)) | ((n) << 15))
+#define POSTDIV1(n)			((0x7 << (12 + 16)) | ((n) << 12))
+#define FBDIV(n)			((0xFFF << 16) | (n))
+
+/* CRU_PLL_CON1 */
+#define RSTMODE(n)			((0x1 << (15 + 16)) | ((n) << 15))
+#define RST(n)				((0x1 << (14 + 16)) | ((n) << 14))
+#define PD(n)				((0x1 << (13 + 16)) | ((n) << 13))
+#define DSMPD(n)			((0x1 << (12 + 16)) | ((n) << 12))
+#define LOCK(n)				(((n) >> 10) & 0x1)
+#define POSTDIV2(n)			((0x7 << (6 + 16)) | ((n) << 6))
+#define REFDIV(n)			((0x3F << 16) | (n))
+
+/* CRU_PLL_CON3 */
+#define SSMOD_SPREAD(n)			((0x1f << (8 + 16)) | ((n) << 8))
+#define SSMOD_DIVVAL(n)			((0xf << (4 + 16)) | ((n) << 4))
+#define SSMOD_DOWNSPREAD(n)		((0x1 << (3 + 16)) | ((n) << 3))
+#define SSMOD_RESET(n)			((0x1 << (2 + 16)) | ((n) << 2))
+#define SSMOD_DIS_SSCG(n)		((0x1 << (1 + 16)) | ((n) << 1))
+#define SSMOD_BP(n)			((0x1 << (0 + 16)) | ((n) << 0))
+
+/* CRU_MODE */
+#define CLOCK_FROM_XIN_OSC		(0)
+#define CLOCK_FROM_PLL			(1)
+#define CLOCK_FROM_RTC_32K		(2)
+#define DPLL_MODE(n)			((0x3 << (2 + 16)) | ((n) << 2))
+
+/* CRU_SOFTRESET_CON1 */
+#define DDRPHY_PSRSTN_REQ(n)		(((0x1 << 14) << 16) | ((n) << 14))
+#define DDRPHY_SRSTN_REQ(n)		(((0x1 << 15) << 16) | ((n) << 15))
+/* CRU_CLKGATE_CON2 */
+#define DDR_MSCH_EN_MASK		((0x1 << 10) << 16)
+#define DDR_MSCH_EN_SHIFT		(10)
+
+/* CRU register */
+#define CRU_PLL_CON(pll_id, n)		((pll_id)  * 0x20 + (n) * 4)
+#define CRU_MODE			(0xa0)
+#define CRU_GLB_CNT_TH			(0xb0)
+#define CRU_CLKSEL_CON_BASE		0x100
+#define CRU_CLKSELS_CON(i)		(CRU_CLKSEL_CON_BASE + ((i) * 4))
+#define CRU_CLKGATE_CON_BASE		0x230
+#define CRU_CLKGATE_CON(i)		(CRU_CLKGATE_CON_BASE + ((i) * 4))
+#define CRU_CLKSFTRST_CON_BASE		0x300
+#define CRU_CLKSFTRST_CON(i)		(CRU_CLKSFTRST_CON_BASE + ((i) * 4))
+
+/* SGRF_SOC_CON2 */
+#define MSCH_AXI_BYPASS_ALL_MASK	(1)
+#define MSCH_AXI_BYPASS_ALL_SHIFT	(15)
+
+/* SGRF_SOC_CON12 */
+#define CLK_DDR_UPCTL_EN_MASK		((0x1 << 2) << 16)
+#define CLK_DDR_UPCTL_EN_SHIFT		(2)
+#define ACLK_DDR_UPCTL_EN_MASK		((0x1 << 0) << 16)
+#define ACLK_DDR_UPCTL_EN_SHIFT		(0)
+
+/* DDRGRF DDR CON2 */
+#define DFI_FREQ_CHANGE_ACK		BIT(10)
+/* DDRGRF status8 */
+#define DFI_FREQ_CHANGE_REQ		BIT(19)
+
+struct rv1126_ddrgrf {
+	u32 ddr_grf_con[4];
+	u32 grf_ddrsplit_con;
+	u32 reserved1[(0x20 - 0x10) / 4 - 1];
+	u32 ddr_grf_lp_con;
+	u32 reserved2[(0x40 - 0x20) / 4 - 1];
+	u32 grf_ddrphy_con[6];
+	u32 reserved3[(0x100 - 0x54) / 4 - 1];
+	u32 ddr_grf_status[18];
+	u32 reserved4[(0x150 - 0x144) / 4 - 1];
+	u32 grf_ddrhold_status;
+	u32 reserved5[(0x160 - 0x150) / 4 - 1];
+	u32 grf_ddrphy_status[2];
+};
+
+struct rv1126_ddr_phy_regs {
+	u32 phy[8][2];
+};
+
+struct msch_regs {
+	u32 coreid;
+	u32 revisionid;
+	u32 deviceconf;
+	u32 devicesize;
+	u32 ddrtiminga0;
+	u32 ddrtimingb0;
+	u32 ddrtimingc0;
+	u32 devtodev0;
+	u32 reserved1[(0x110 - 0x20) / 4];
+	u32 ddrmode;
+	u32 ddr4timing;
+	u32 reserved2[(0x1000 - 0x118) / 4];
+	u32 agingx0;
+	u32 reserved3[(0x1040 - 0x1004) / 4];
+	u32 aging0;
+	u32 aging1;
+	u32 aging2;
+	u32 aging3;
+};
+
+struct sdram_msch_timings {
+	union noc_ddrtiminga0 ddrtiminga0;
+	union noc_ddrtimingb0 ddrtimingb0;
+	union noc_ddrtimingc0 ddrtimingc0;
+	union noc_devtodev_rv1126 devtodev0;
+	union noc_ddrmode ddrmode;
+	union noc_ddr4timing ddr4timing;
+	u32 agingx0;
+	u32 aging0;
+	u32 aging1;
+	u32 aging2;
+	u32 aging3;
+};
+
+struct rv1126_sdram_channel {
+	struct sdram_cap_info cap_info;
+	struct sdram_msch_timings noc_timings;
+};
+
+struct rv1126_sdram_params {
+	struct rv1126_sdram_channel ch;
+	struct sdram_base_params base;
+	struct ddr_pctl_regs pctl_regs;
+	struct rv1126_ddr_phy_regs phy_regs;
+};
+
+struct rv1126_fsp_param {
+	u32 flag;
+	u32 freq_mhz;
+
+	/* dram size */
+	u32 dq_odt;
+	u32 ca_odt;
+	u32 ds_pdds;
+	u32 vref_ca[2];
+	u32 vref_dq[2];
+
+	/* phy side */
+	u32 wr_dq_drv;
+	u32 wr_ca_drv;
+	u32 wr_ckcs_drv;
+	u32 rd_odt;
+	u32 rd_odt_up_en;
+	u32 rd_odt_down_en;
+	u32 vref_inner;
+	u32 vref_out;
+	u32 lp4_drv_pd_en;
+
+	struct sdram_msch_timings noc_timings;
+};
+
+#define MAX_IDX			(4)
+#define FSP_FLAG		(0xfead0001)
+#define SHARE_MEM_BASE		(0x100000)
+/*
+ * Borrow share memory space to temporarily store FSP parame.
+ * In the stage of DDR init write FSP parame to this space.
+ * In the stage of trust init move FSP parame to SRAM space
+ * from share memory space.
+ */
+#define FSP_PARAM_STORE_ADDR	(SHARE_MEM_BASE)
+
+/* store result of read and write training, for ddr_dq_eye tool in u-boot */
+#define RW_TRN_RESULT_ADDR	(0x2000000 + 0x8000)	/* 32M + 32k */
+#define PRINT_STEP		1
+
+#undef FSP_NUM
+#undef CS_NUM
+#undef BYTE_NUM
+
+#define FSP_NUM			4
+#define CS_NUM			2
+#define BYTE_NUM		4
+#define RD_DESKEW_NUM		64
+#define WR_DESKEW_NUM		64
+
+#define LP4_WIDTH_REF_MHZ_H	1056
+#define LP4_RD_WIDTH_REF_H	12
+#define LP4_WR_WIDTH_REF_H	13
+
+#define LP4_WIDTH_REF_MHZ_L	924
+#define LP4_RD_WIDTH_REF_L	15
+#define LP4_WR_WIDTH_REF_L	15
+
+#define DDR4_WIDTH_REF_MHZ_H	1056
+#define DDR4_RD_WIDTH_REF_H	13
+#define DDR4_WR_WIDTH_REF_H	9
+
+#define DDR4_WIDTH_REF_MHZ_L	924
+#define DDR4_RD_WIDTH_REF_L	15
+#define DDR4_WR_WIDTH_REF_L	11
+
+#define LP3_WIDTH_REF_MHZ_H	1056
+#define LP3_RD_WIDTH_REF_H	15
+#define LP3_WR_WIDTH_REF_H	13
+
+#define LP3_WIDTH_REF_MHZ_L	924
+#define LP3_RD_WIDTH_REF_L	16
+#define LP3_WR_WIDTH_REF_L	15
+
+#define DDR3_WIDTH_REF_MHZ_H	1056
+#define DDR3_RD_WIDTH_REF_H	14
+#define DDR3_WR_WIDTH_REF_H	14
+
+#define DDR3_WIDTH_REF_MHZ_L	924
+#define DDR3_RD_WIDTH_REF_L	17
+#define DDR3_WR_WIDTH_REF_L	17
+
+#endif /* _ASM_ARCH_SDRAM_RK1126_H */