diff options
| author | Andre Przywara | 2017-01-02 11:48:43 +0000 |
|---|---|---|
| committer | Jagan Teki | 2017-01-04 16:37:43 +0100 |
| commit | ed25486215148cb0a8ed4459aa74d04bacbcd3c3 (patch) | |
| tree | 94a874ac888cf95b5d48bfbf007e55a495abdd78 /arch | |
| parent | 1bc464be1fc559a3f6dc1334297245d5b27b9b57 (diff) | |
sunxi: H3/A64: fix non-ODT setting
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sun8i_h3.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c index fe9cf9a181b..1311edaf325 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -414,6 +414,11 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para) udelay(500); } +/* These are more guessed based on some Allwinner code. */ +#define DX_GCR_ODT_DYNAMIC (0x0 << 4) +#define DX_GCR_ODT_ALWAYS_ON (0x1 << 4) +#define DX_GCR_ODT_OFF (0x2 << 4) + static int mctl_channel_init(uint16_t socid, struct dram_para *para) { struct sunxi_mctl_com_reg * const mctl_com = @@ -443,7 +448,8 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) | (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | (0x3 << 14), - IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); + IS_ENABLED(CONFIG_DRAM_ODT_EN) ? + DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF); /* AC PDR should always ON */ setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); |