diff options
| author | Svyatoslav Ryhel | 2024-01-17 18:32:21 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel | 2024-04-22 12:17:20 +0300 |
| commit | edad9f6b55930370ec96b24c0b634dc9cae13c4e (patch) | |
| tree | 780545f9fe873fc1d38dd2e1e83db143a5eaf328 /arch | |
| parent | ed5b2b105edd310e31d85b0338ada9a073c2b2ce (diff) | |
board: asus: tf600t: configure SPI pinmux
Unlike all other transformers, TF600T has an SPI flash to store
boot firmware and requires precise SPI pinmux configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/tegra30-asus-tf600t.dts | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index f49e7341fe0..86ad925921f 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -469,6 +469,42 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; + /* SPI pinmux */ + spi1_ctrl { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_sck { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs1_n { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi4_ctrl { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + /* Display A pinmux */ lcd_pwr0_pb2 { nvidia,pins = "lcd_pwr0_pb2", |