diff options
| author | Tom Rini | 2022-10-07 11:25:05 -0400 |
|---|---|---|
| committer | Tom Rini | 2022-10-07 11:25:05 -0400 |
| commit | f5717231abad983b4d8f87db612ae60dec86cb1b (patch) | |
| tree | 4a3fa6357741a3739fc5ca159228d25ff5f87bb8 /arch | |
| parent | 5c3801df300e28fc59bc66fde9b5ba488b6bdd9a (diff) | |
| parent | 1dde977518f13824b847e23275001191139bc384 (diff) | |
Merge branch '2022-10-07-riscv-toolchain-update'
- Update RISC-V to use 32bit or 64bit toolchains, depending on if we're
building for 32bit or 64bit CPUs. This requires updating the Docker
container as well to have the 32bit toolchain.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/Makefile | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d864..53d1194ffb6 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) +ifeq ($(toolchain-need-zicsr-zifencei),y) + RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei +endif + +ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) |