diff options
| author | Michal Simek | 2023-09-27 11:53:33 +0200 |
|---|---|---|
| committer | Michal Simek | 2023-10-09 12:12:30 +0200 |
| commit | fa822ad19e97af1176212f0f9f980f8061a39572 (patch) | |
| tree | 2677efc4bf6fa9adedc2cf685c903c0dc1a5e277 /arch | |
| parent | 64f5e3b4924781890c6913fd2537563df28b1ced (diff) | |
arm64: zynqmp: Add support for SC revC
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sc-revC.dts | 37 |
2 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 29c40d1c3b6..3cde86d9eb3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -412,6 +412,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ zynqmp-sc-revB.dtb \ + zynqmp-sc-revC.dtb \ zynqmp-sm-k24-revA.dtb \ zynqmp-smk-k24-revA.dtb \ zynqmp-sm-k26-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts new file mode 100644 index 00000000000..530a4a5f080 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-revC.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP Generic System Controller + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include "zynqmp-sc-revB.dts" + +/ { + model = "ZynqMP Generic System Controller"; + compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; +}; + +&gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ + /delete-node/ mdio; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@1 { /* ADI1300 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id0283.bc30"; + reg = <1>; + adi,rx-internal-delay-ps = <2400>; + adi,tx-internal-delay-ps = <2400>; + adi,fifo-depth-bits = <8>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + }; + }; +}; |