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authorHou Zhiqiang2016-12-16 17:15:46 +0800
committerYork Sun2017-01-18 09:27:27 -0800
commit3b6bf8115ff2d85caa5b0af366b7053d5c7822fd (patch)
tree22c588cfa35f95d89062d5aa49316033181f38c6 /board/coreboot
parent6930be345aab208ac22ace91eea6790a13b46262 (diff)
armv8/fsl_lsch2: Add the OCRAM initialization
Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/coreboot')
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