diff options
| author | Fabio Estevam | 2011-10-20 16:01:31 +0000 |
|---|---|---|
| committer | Albert ARIBAUD | 2011-11-03 22:56:18 +0100 |
| commit | 199222fcd280dc7abde193e0ba4a649c5cc32fbb (patch) | |
| tree | df38692a296bb6e5cad5c464be5cc90bea4eb1ca /board/davedenx | |
| parent | 842d853adad65d469de47c7826866dfade4c38c4 (diff) | |
qong: remove unneeded IOMUX settings
On qong board some of the USBH2 pins are set via GPR register, so don need to setup
the IOMUX for each pin individually.
Other than that, these pins should not be configured as primary function because the primary
function selects SSI functionality.
Let GPR register do the work and remove the unneeded IOMUX setup.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/davedenx')
| -rw-r--r-- | board/davedenx/qong/qong.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 3f6e0c28242..665aedf0b5f 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -120,12 +120,6 @@ int board_early_init_f(void) mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) |