diff options
| author | Claudiu Manoil | 2015-08-12 13:29:14 +0300 |
|---|---|---|
| committer | York Sun | 2015-09-01 21:39:03 -0500 |
| commit | ebe4c1e6469444753bd2ba93fe63e6183cf2905c (patch) | |
| tree | cec6f84bbbdf284f6abceb121663b07b2f4b2a61 /board/freescale/ls1021atwr | |
| parent | da2919b4a904411c374a6e0d9dc771e180968266 (diff) | |
ls102xa: etsec: Use proper settings for BE BDs
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.
Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1021atwr')
| -rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9e995..006700f420f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -481,7 +481,8 @@ int board_early_init_f(void) unsigned int major; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif |