rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

2 files changed, 20 insertions, 20 deletions

diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 768f40bb0aa..088c8c4d1ac 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -49,16 +49,16 @@ phys_size_t initdram(int board_type)
 	 * Serial Boot: The dram is already initialized in start.S
 	 * only require to return DRAM size
 	 */
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 #else
 	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
 	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
 	u32 i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
-	if ((sdram->sdcfg1 == CFG_SDRAM_CFG1) &&
-	    (sdram->sdcfg2 == CFG_SDRAM_CFG2))
+	if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
+	    (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
 		return dramsize;
 
 	for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +67,32 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
 
-	sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CFG_SDRAM_CFG1;
-	sdram->sdcfg2 = CFG_SDRAM_CFG2;
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	udelay(200);
 
 	/* Issue PALL */
-	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
 	__asm__("nop");
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
 	__asm__("nop");
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
 	__asm__("nop");
 
 	/* Issue LEMR */
-	sdram->sdmr = CFG_SDRAM_MODE;
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
 	__asm__("nop");
-	sdram->sdmr = CFG_SDRAM_EMOD;
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
 	__asm__("nop");
 
-	sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
 
 	udelay(100);
 #endif
diff --git a/board/freescale/m54451evb/mii.c b/board/freescale/m54451evb/mii.c
index 5a4330c74a6..6e24736f181 100644
--- a/board/freescale/m54451evb/mii.c
+++ b/board/freescale/m54451evb/mii.c
@@ -43,7 +43,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
 		else
 			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
@@ -51,7 +51,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 		gpio->par_feci2c &=
 		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
 		else
 			gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
@@ -59,7 +59,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -135,9 +135,9 @@ uint mii_send(uint mii_cmd)
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -202,7 +202,7 @@ int mii_discover_phy(struct eth_device *dev)
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__ ((weak, alias("__mii_init")));