diff options
| author | Shengzhou Liu | 2014-11-14 10:31:22 +0800 |
|---|---|---|
| committer | York Sun | 2014-12-05 08:06:14 -0800 |
| commit | 06b3acf1848b48f127952f609115a994fefbd520 (patch) | |
| tree | 53cc9f5435e295c20e76e3fd6c7368d2b90567ed /board/freescale/t208xrdb | |
| parent | e2544e7a5459b7ad5efd8c99d54e71c2535281d1 (diff) | |
powerpc/t2080: updating rcw for silicon v1.1
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
We reserve the support for T2080 v1.0 and enable v1.1 by default.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t208xrdb')
| -rw-r--r-- | board/freescale/t208xrdb/t2080_rcw.cfg | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg index 15e1bf43dd6..59025eaf1e9 100644 --- a/board/freescale/t208xrdb/t2080_rcw.cfg +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -1,8 +1,16 @@ -#PBL preamble and RCW header for T2080RDB +#PBL preamble and RCW header aa55aa55 010e0100 -#SerDes Protocol: 0x66_0x16 -#Core/DDR: 1533Mhz/1600MT/s -120c0017 15000000 00000000 00000000 -66150002 00008400 ec104000 c1000000 -00000000 00000000 00000000 000307fc + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s +#120c0017 15000000 00000000 00000000 +#66150002 00008400 ec104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s +1206001b 15000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 +00800000 00000000 00000000 000307fc 00000000 00000000 00000000 00000004 |