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authorYork Sun2017-12-05 10:57:54 -0800
committerYork Sun2017-12-06 14:54:12 -0800
commit316f0d0f8f3cbeeefda043e69f3e4e6aa57f7f1d (patch)
treee4201de6e106653a02a04c13f21cf3685bc878ee /board/freescale
parent0f2296bab1417faa5973e6d6690c8be0f83ecd08 (diff)
powerpc: mpc85xx: Fix static TLB table for SDRAM
Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/b4860qds/tlb.c2
-rw-r--r--board/freescale/bsc9131rdb/tlb.c2
-rw-r--r--board/freescale/bsc9132qds/tlb.c2
-rw-r--r--board/freescale/c29xpcie/tlb.c4
-rw-r--r--board/freescale/mpc8541cds/tlb.c2
-rw-r--r--board/freescale/mpc8548cds/tlb.c2
-rw-r--r--board/freescale/mpc8568mds/tlb.c2
-rw-r--r--board/freescale/p1010rdb/tlb.c2
-rw-r--r--board/freescale/p1022ds/tlb.c4
-rw-r--r--board/freescale/p1023rdb/tlb.c4
-rw-r--r--board/freescale/p1_p2_rdb_pc/tlb.c2
-rw-r--r--board/freescale/p1_twr/tlb.c2
-rw-r--r--board/freescale/t102xqds/tlb.c4
-rw-r--r--board/freescale/t102xrdb/tlb.c4
-rw-r--r--board/freescale/t104xrdb/tlb.c4
-rw-r--r--board/freescale/t208xqds/tlb.c2
-rw-r--r--board/freescale/t208xrdb/tlb.c2
-rw-r--r--board/freescale/t4qds/tlb.c2
-rw-r--r--board/freescale/t4rdb/tlb.c2
19 files changed, 25 insertions, 25 deletions
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 7b55b860d08..88910d6cd11 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -147,7 +147,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 17, BOOKE_PAGESZ_2G, 1)
#endif
};
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index c8ecf5de591..e5dab9ea30d 100644
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 07febc2b375..56199e52449 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -71,7 +71,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index c5abed05049..85d58c8cd45 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -67,11 +67,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
index fff3b4a7c28..6664f2755d3 100644
--- a/board/freescale/mpc8541cds/tlb.c
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* 0xf000_0000 64M LBC SDRAM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 6, BOOKE_PAGESZ_64M, 1),
/*
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 363e043d068..571341ff68e 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -48,7 +48,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 2, BOOKE_PAGESZ_64M, 1),
/*
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index b5e2fec1f99..03d0fa1cd9a 100644
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* 0xf000_0000 64M LBC SDRAM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 4, BOOKE_PAGESZ_64M, 1),
/*
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index af40f979d36..7d151f9e5f3 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index e7ae2e25b22..69d5e449e0d 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -75,12 +75,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* **** - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
index 8fd178e211b..35a63fe0269 100644
--- a/board/freescale/p1023rdb/tlb.c
+++ b/board/freescale/p1023rdb/tlb.c
@@ -86,12 +86,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_SYS_RAMBOOT
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_256M, 1),
#endif
};
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 7cba411007f..6324ebfa322 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
index 308335c974a..0f365f91634 100644
--- a/board/freescale/p1_twr/tlb.c
+++ b/board/freescale/p1_twr/tlb.c
@@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_SYS_RAMBOOT
/* *I*G - eSDHC boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
index 409e1739996..0d27a998c51 100644
--- a/board/freescale/t102xqds/tlb.c
+++ b/board/freescale/t102xqds/tlb.c
@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 8269b3d7250..d77ce25784c 100644
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c
@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 7c0511e268b..078947902fd 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -120,11 +120,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
};
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index 8d602989b2d..b0b3b4d48a5 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -145,7 +145,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 2ebea36a5c2..2cae4d02b36 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -144,7 +144,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 1e4d096f5f9..a6d8bb36037 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -139,7 +139,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
#endif
};
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index 6a6b4b5cc13..648cfabeea0 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -116,7 +116,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 18, BOOKE_PAGESZ_2G, 1)
#endif
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 23:40:01 +0000