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| author | Lokesh Vutla | 2016-11-03 15:35:02 +0530 |
|---|---|---|
| committer | Tom Rini | 2016-11-13 15:54:37 -0500 |
| commit | 4d0fec0e69189bd81c09909fc4eb742c63d5d7ee (patch) | |
| tree | aa0689931712615a5c9d2292f7383e1d404816ea /board/freescale | |
| parent | 8b01ebd8128821febd84ee0f413c16d6339678d6 (diff) | |
ARM: k2g: Update PLL Multiplier and divider values
Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18
[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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