ppc4xx: Add DLVision-10G board support

Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

5 files changed, 310 insertions, 39 deletions

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd2330943..86a3ec882b9 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,8 +26,9 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
 
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
 
 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
@@ -36,8 +37,29 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
 int board_early_init_f(void)
 {
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->fpga_state[k] = 0;
+
 	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
 	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
@@ -66,10 +88,18 @@ int board_early_init_f(void)
 
 	/*
 	 * wait for fpga-done
-	 * fail ungraceful if fpga is not configuring properly
 	 */
-	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
-		;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!(in_le16((void *)LATCH2_BASE)
+			& CONFIG_SYS_FPGA_DONE(k))) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
 
 	/*
 	 * setup io-latches for boot (stop reset)
@@ -78,15 +108,25 @@ int board_early_init_f(void)
 	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 
-	/*
-	 * wait for fpga out of reset
-	 * fail ungraceful if fpga is not working properly
-	 */
-	while (1) {
-		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
-		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
-			REFLECTION_TESTPATTERN_INV)
-			break;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			out_le16(&fpga->reflection_low,
+				REFLECTION_TESTPATTERN);
+			if (in_le16(&fpga->reflection_high) ==
+				REFLECTION_TESTPATTERN_INV)
+				break;
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
 	}
 
 	return 0;
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index ed3120784b9..169418c288e 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS-$(CONFIG_IO) += io.o
 COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
 
 COBJS   := $(BOARD).o $(COBJS-y)
 SOBJS   =
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 00000000000..df7fb143c43
--- /dev/null
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+enum {
+	UNITTYPE_VIDEO_USER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+	HWVER_101 = 0,
+	HWVER_110 = 1,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_156250 = 2,
+};
+
+enum {
+	RAM_NONE = 0,
+	RAM_DDR2_32 = 1,
+	RAM_DDR2_64 = 2,
+};
+
+static void print_fpga_info(unsigned dev)
+{
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_rs232;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+	int fpga_state = get_fpga_state(dev);
+
+	printf("FPGA%d: ", dev);
+
+	hardware_version = versions & 0x000f;
+
+	if (fpga_state
+	    && !((hardware_version == HWVER_101)
+		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+		puts("not available\n");
+		print_fpga_state(dev);
+		return;
+	}
+
+	unit_type = (versions >> 4) & 0x000f;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features >> 13) & 0x0003;
+	feature_rs232 = fpga_features & (1<<11);
+	feature_audio = (fpga_features >> 9) & 0x0003;
+	feature_sysclock = (fpga_features >> 7) & 0x0003;
+	feature_ramconfig = (fpga_features >> 5) & 0x0003;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features >> 2) & 0x0003;
+	feature_video_channels = fpga_features & 0x0003;
+
+	switch (unit_type) {
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel Userside");
+		break;
+
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel Userside");
+		break;
+
+	case UNITTYPE_VIDEO_SERVER:
+		printf("Videochannel Serverside");
+		break;
+
+	case UNITTYPE_MAIN_SERVER:
+		printf("Mainchannel Serverside");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_101:
+		printf(" HW-Ver 1.01\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	switch (feature_sysclock) {
+	case SYSCLK_156250:
+		printf(", clock 156.25 MHz");
+		break;
+
+	default:
+		printf(", clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_ramconfig) {
+	case RAM_NONE:
+		printf("no RAM");
+		break;
+
+	case RAM_DDR2_32:
+		printf("RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR2_64:
+		printf("RAM 64 bit DDR2");
+		break;
+
+	default:
+		printf("RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+		feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	unsigned k;
+	char *s = getenv("serial#");
+
+	printf("Board: ");
+
+	printf("DLVision 10G");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		print_fpga_info(k);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
+		if (!get_fpga_state(k)
+		    || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
+			osd_probe(k);
+
+	return 0;
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 80877b61ffa..0974019ef7f 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -29,7 +29,7 @@
 
 #include <miiphy.h>
 
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
 
 #define PHYREG_CONTROL				0
 #define PHYREG_PAGE_ADDRESS			22
@@ -37,13 +37,6 @@
 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
 
 enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_FEATURES = 0x0004,
-	REG_FPGA_VERSION = 0x0006,
-	REG_QUAD_SERDES_RESET = 0x0012,
-};
-
-enum {
 	UNITTYPE_CCD_SWITCH = 1,
 };
 
@@ -94,10 +87,11 @@ err_out:
  */
 int checkboard(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_channels;
@@ -166,6 +160,7 @@ int checkboard(void)
  */
 int last_stage_init(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	unsigned int k;
 
 	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
@@ -175,7 +170,7 @@ int last_stage_init(void)
 		configure_gbit_phy(k);
 
 	/* take fpga serdes blocks out of reset */
-	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+	out_le16(&fpga->quad_serdes_reset, 0);
 
 	return 0;
 }
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ecd6cb2396c..20770e4eff9 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -27,14 +27,9 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
-#include "../common/fpga.h"
-#include "../common/osd.h"
+#include <gdsys_fpga.h>
 
-enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_VERSION = 0x0004,
-	REG_FPGA_FEATURES = 0x0006,
-};
+#include "../common/osd.h"
 
 enum {
 	UNITTYPE_MAIN_SERVER = 0,
@@ -74,10 +69,11 @@ enum {
  */
 int checkboard(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_compression;
@@ -214,7 +210,7 @@ int checkboard(void)
 
 int last_stage_init(void)
 {
-	return osd_probe();
+	return osd_probe(0);
 }
 
 /*
@@ -222,15 +218,15 @@ int last_stage_init(void)
  */
 void fpga_gpio_set(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
 }
 
 void fpga_gpio_clear(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
 }
 
 int fpga_gpio_get(int pin)
 {
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }