diff options
| author | Dirk Eibach | 2015-10-28 11:46:27 +0100 |
|---|---|---|
| committer | Tom Rini | 2015-11-12 15:59:03 -0500 |
| commit | d054c2f8c6af6df672bbbb524252c4f5c1d4bf45 (patch) | |
| tree | 6a1056bdbb3e9a5ab335ba704f7b8eaed6715529 /board/gdsys | |
| parent | 2302fd32a5c2015be204e71737481322fe7b5f3a (diff) | |
board: gdsys: Consider DP501 limits on link training
DP501 only supports DP 1.1a.
Limit settings for link bandwidth and lane count to
values allowed by DP 1.1a.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Diffstat (limited to 'board/gdsys')
| -rw-r--r-- | board/gdsys/common/dp501.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 0389fd1750a..d35aee0879f 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -40,11 +40,29 @@ static int dp501_detect_cable_adapter(u8 addr) static void dp501_link_training(u8 addr) { u8 val; + u8 link_bw; + u8 max_lane_cnt; + u8 lane_cnt; val = i2c_reg_read(addr, 0x51); - i2c_reg_write(addr, 0x5d, val); /* set link_bw */ + if (val >= 0x0a) + link_bw = 0x0a; + else + link_bw = 0x06; + if (link_bw != val) + printf("DP sink supports %d Mbps link rate, set to %d Mbps\n", + val * 270, link_bw * 270); + i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */ val = i2c_reg_read(addr, 0x52); - i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */ + max_lane_cnt = val & 0x1f; + if (max_lane_cnt >= 4) + lane_cnt = 4; + else + lane_cnt = max_lane_cnt; + if (lane_cnt != max_lane_cnt) + printf("DP sink supports %d lanes, set to %d lanes\n", + max_lane_cnt, lane_cnt); + i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ val = i2c_reg_read(addr, 0x53); i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */ |