diff options
| author | Stefan Roese | 2009-09-09 16:25:29 +0200 |
|---|---|---|
| committer | Stefan Roese | 2009-09-11 10:35:58 +0200 |
| commit | d1c3b27525b664e8c4db6bb173eed51bfc8220de (patch) | |
| tree | c00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/prodrive/p3p440 | |
| parent | e7963772eb78a6aa1fa65063d64eab3a8626daac (diff) | |
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/prodrive/p3p440')
| -rw-r--r-- | board/prodrive/p3p440/p3p440.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 1a0486f5c0c..18054e45b6e 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -85,14 +85,14 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * Setup pin multiplexing (GPIO/IRQ...) *-------------------------------------------------------------------*/ - mtdcr(cpc0_gpio, 0x03F01F80); + mtdcr(CPC0_GPIO, 0x03F01F80); out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); @@ -153,12 +153,12 @@ int misc_init_r (void) * Check if only one FLASH bank is available */ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - mtebc(pb1cr, 0); /* disable cs */ - mtebc(pb1ap, 0); - mtebc(pb2cr, 0); /* disable cs */ - mtebc(pb2ap, 0); - mtebc(pb3cr, 0); /* disable cs */ - mtebc(pb3ap, 0); + mtebc(PB1CR, 0); /* disable cs */ + mtebc(PB1AP, 0); + mtebc(PB2CR, 0); /* disable cs */ + mtebc(PB2AP, 0); + mtebc(PB3CR, 0); /* disable cs */ + mtebc(PB3AP, 0); } return 0; @@ -185,7 +185,7 @@ int pci_pre_init(struct pci_controller *hose) * The P3P440 board is always configured as the host & requires the * PCI arbiter to be disabled because it's an PMC module. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if (strap & 0x00100000) { printf("PCI: CPC0_STRP1[PAE] set.\n"); return 0; |