diff options
| author | Hiroyuki Yokoyama | 2017-03-23 10:35:41 +0900 |
|---|---|---|
| committer | Marek Vasut | 2018-10-18 19:07:46 +0200 |
| commit | 4cb71e248f4cee437a5913d0d618f62058ea36ef (patch) | |
| tree | 1ae208c116b9617be64603832f0eca4e1ab2aad6 /board/renesas | |
| parent | a14d2d153db7b42b9ad0b03a7b772b32bbd8746f (diff) | |
ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3
Tidy up unused definition related to power control of 3DG.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Diffstat (limited to 'board/renesas')
| -rw-r--r-- | board/renesas/draak/draak.c | 6 | ||||
| -rw-r--r-- | board/renesas/salvator-x/salvator-x.c | 6 | ||||
| -rw-r--r-- | board/renesas/ulcb/ulcb.c | 6 |
3 files changed, 0 insertions, 18 deletions
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 71fd5001c45..060343dfe4d 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -44,12 +44,6 @@ int board_early_init_f(void) return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#define SYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#define SYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 726a236af36..a1a15316639 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -44,12 +44,6 @@ int board_early_init_f(void) return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#define SYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#define SYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index a7ca274f34c..e549a2efac9 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -44,12 +44,6 @@ int board_early_init_f(void) return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#define SYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#define SYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) |