rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

3 files changed, 17 insertions, 17 deletions

diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk
index 91aee2fc7de..565e826b80c 100644
--- a/board/sandburst/metrobox/config.mk
+++ b/board/sandburst/metrobox/config.mk
@@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
index e398f0008d7..ccdec46ee54 100644
--- a/board/sandburst/metrobox/init.S
+++ b/board/sandburst/metrobox/init.S
@@ -88,12 +88,12 @@
 tlbtab:
 	tlbtab_start
 	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
 	tlbtab_end
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index c38850d6c74..c3c44593a80 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -55,7 +55,7 @@ int board_early_init_f (void)
 	mtsdr(sdr_pfc0, 0x00103E00);
 
 	/* Setup access for LEDs, and system topology info */
-	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
 	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
 	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
 
@@ -83,7 +83,7 @@ int board_early_init_f (void)
 	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 	      EBC_BXAP_PEN_DISABLED);
 
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
 	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 	/*--------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -246,7 +246,7 @@ int checkboard (void)
 	unsigned char opto_rev, opto_id;
 	OPTO_FPGA_REGS_ST *opto_ps;
 
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	opto_rev = (unsigned char)((opto_ps->revision_ul &
 				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
@@ -286,7 +286,7 @@ int checkboard (void)
 
 	/* Fix the ack in the bme 32 */
 	udelay(5000);
-	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 	asm("eieio");
 
 
@@ -302,7 +302,7 @@ int misc_init_f (void)
 {
 	/* Turn on i2c bus 1 */
 	puts ("I2C1:  ");
-	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	puts ("ready\n");
 
 	/* Turn on fans */
@@ -323,7 +323,7 @@ int misc_init_r (void)
 	unsigned char opto_rev;
 	OPTO_FPGA_REGS_ST *opto_ps;
 
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	if(NULL != getenv("secondserial")) {
 	    puts("secondserial is set, switching to second serial port\n");
@@ -387,7 +387,7 @@ int misc_init_r (void)
 void ide_set_reset(int on)
 {
 	OPTO_FPGA_REGS_ST *opto_ps;
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	if (on) {		/* assert RESET */
 	    opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
@@ -412,7 +412,7 @@ void fpga_init(void)
 	/*
 	 * Take appropriate hw bits out of reset
 	 */
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	tmp =
 	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |