diff options
| author | Masahiro Yamada | 2014-01-08 20:11:02 +0900 |
|---|---|---|
| committer | Tom Rini | 2014-01-24 16:59:07 -0500 |
| commit | 853ce2ee9c53b97694804e60450c15d40df9b502 (patch) | |
| tree | edad35df251b7564c6a0f7c827c4fd38bfdebd5b /board/sandpoint | |
| parent | df05ff77891ff94c03acdd984d85c04e0b374ae9 (diff) | |
board: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/sandpoint')
| -rw-r--r-- | board/sandpoint/speed.h | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h deleted file mode 100644 index f1b10bf25ee..00000000000 --- a/board/sandpoint/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ |