diff options
| author | Peter Tyser | 2008-11-11 10:17:10 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING | 2008-12-03 22:46:42 -0600 |
| commit | a2cd50ed6ef0ac6b127b3d6db756979a8336718d (patch) | |
| tree | a8064eb08a501fdecadfb50af56f646c90be0f3a /board/sbc8548 | |
| parent | e57f0fa1333cdf3ca36110aac2900712a5f82976 (diff) | |
85xx: Add CPU 2 errata workaround to all 8548 boards
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/sbc8548')
| -rw-r--r-- | board/sbc8548/sbc8548.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index cfb9ce5144f..017f6b35cf6 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -62,13 +62,6 @@ int checkboard (void) local_bus_init (); /* - * Fix CPU2 errata: A core hang possible while executing a - * msync instruction and a snoopable transaction from an I/O - * master tagged to make quick forward progress is present. - */ - ecm->eebpcr |= (1 << 16); - - /* * Hack TSEC 3 and 4 IO voltages. */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ |