diff options
| author | Patrick Delaunay | 2019-08-01 11:29:03 +0200 |
|---|---|---|
| committer | Joe Hershberger | 2019-09-04 11:37:19 -0500 |
| commit | 53e3d52c6cd628c6ff1ebe6695a38014f8241ed6 (patch) | |
| tree | 29aac96f3f3bb1d121200081331d50d2bc8f8f57 /board/st | |
| parent | 50d86e55a4e1dd208109877d4cad21ef504736b9 (diff) | |
net: dwc_et_qos: update weak function board_interface_eth_init
Align the board and driver prototype for board_interface_eth_init
to avoid execution issue (the interface_type parameter is defined
as int or phy_interface_t).
To have a generic weak function (it should be reused by other driver)
I change the prototype to use directly udevice.
This prototype is added in netdev.h to allow compilation check
and avoid warning when compiling with W=1 on file
board/st/stm32mp1/stm32mp1.c
warning: no previous prototype for 'board_interface_eth_init'\
[-Wmissing-prototypes]
int board_interface_eth_init(int interface_type, ....
^~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'board/st')
| -rw-r--r-- | board/st/stm32mp1/stm32mp1.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index fc14ad375c8..18f9b848765 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -17,6 +17,7 @@ #include <misc.h> #include <mtd.h> #include <mtd_node.h> +#include <netdev.h> #include <phy.h> #include <remoteproc.h> #include <reset.h> @@ -683,12 +684,21 @@ void board_quiesce_devices(void) #endif } -/* board interface eth init */ -int board_interface_eth_init(phy_interface_t interface_type, - bool eth_clk_sel_reg, bool eth_ref_clk_sel_reg) +/* eth init function : weak called in eqos driver */ +int board_interface_eth_init(struct udevice *dev, + phy_interface_t interface_type) { u8 *syscfg; u32 value; + bool eth_clk_sel_reg = false; + bool eth_ref_clk_sel_reg = false; + + /* Gigabit Ethernet 125MHz clock selection. */ + eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + + /* Ethernet 50Mhz RMII clock selection */ + eth_ref_clk_sel_reg = + dev_read_bool(dev, "st,eth_ref_clk_sel"); syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); |