diff options
| author | pekon gupta | 2013-11-18 19:03:02 +0530 |
|---|---|---|
| committer | Scott Wood | 2013-11-21 13:33:41 -0600 |
| commit | 2c17e6d1d996a1b8b9325de15f253a13d5877dee (patch) | |
| tree | 5404e5dea7c6e046fdaaa07fa98f4231c6fc1340 /board/ti | |
| parent | 3f719069c884284b2457448a7afe32b02bd4f782 (diff) | |
am335x: fix GPMC config for NAND and NOR SPL boot
GPMC controller is common IP to interface with both NAND and NOR flash devices.
Also, it supports max 8 chip-selects, which can be independently connected to
any of the devices.
But ROM code expects the boot-device to be connected to only chip-select[0].
Thus to resolve conflict between NOR and NAND boot. This patch:
- combines NOR and NAND configs spread in board files to common gpmc_init()
- configures GPMC based on boot-mode selected for SPL boot.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Diffstat (limited to 'board/ti')
| -rw-r--r-- | board/ti/am335x/board.c | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57fedab340a..0299dd6486f 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -481,26 +481,14 @@ void sdram_init(void) */ int board_init(void) { -#ifdef CONFIG_NOR - const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; -#endif - #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); - -#ifdef CONFIG_NOR - /* Reconfigure CS0 for NOR instead of NAND. */ - enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], - CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); #endif - return 0; } |