diff options
| author | Francesco Dolcini | 2021-08-31 11:46:05 +0200 |
|---|---|---|
| committer | Stefano Babic | 2021-10-19 10:51:39 +0200 |
| commit | 1194d1711781fe30bf664c1bf2d559ffa76ccc7e (patch) | |
| tree | 322b68525325e182546367ec8086b86cd9586ea3 /board/toradex | |
| parent | fa0223a75946ad3aec2596dac34d88f2dcca7baa (diff) | |
colibri-imx6: use dynamic DDR calibration
Enable dynamic DDR calibration to have a reliable behavior on edge
temperatures conditions.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Diffstat (limited to 'board/toradex')
| -rw-r--r-- | board/toradex/colibri_imx6/colibri_imx6.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 3b55f6c938e..38ff637054a 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -997,9 +997,28 @@ static void ddr_init(int *table, int size) writel(table[2 * i + 1], table[2 * i]); } +/* Perform DDR DRAM calibration */ +static void spl_dram_perform_cal(u8 dsize) +{ +#ifdef CONFIG_MX6_DDRCAL + int err; + struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = dsize, + }; + + err = mmdc_do_write_level_calibration(&ddr_sysinfo); + if (err) + printf("error %d from write level calibration\n", err); + err = mmdc_do_dqs_calibration(&ddr_sysinfo); + if (err) + printf("error %d from dqs calibration\n", err); +#endif +} + static void spl_dram_init(void) { int minc, maxc; + u8 dsize = 2; switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_COMMERCIAL: @@ -1009,6 +1028,7 @@ static void spl_dram_init(void) ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); + dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; @@ -1020,11 +1040,13 @@ static void spl_dram_init(void) ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); + dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; }; udelay(100); + spl_dram_perform_cal(dsize); } static iomux_v3_cfg_t const gpio_reset_pad[] = { |