diff options
| author | Jagan Teki | 2020-05-09 22:26:24 +0530 |
|---|---|---|
| committer | Kever Yang | 2020-05-22 20:53:20 +0800 |
| commit | 0672e9803b88cbc8268ee65120cfa27fe8e2fb82 (patch) | |
| tree | b6571b0463b336c4ebdcd30dab0cf0912d3f7e47 /board/vamrs | |
| parent | 765a12d6a39ee2151421c5fc0250d9eefdf0e085 (diff) | |
rockchip: Enable PCIe/M.2 on rock960 board
Due to board limitation some SSD's would work
on rock960 PCIe M.2 only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly to
make PCIe/M.2 to work.
Cc: Tom Cubie <tom@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'board/vamrs')
| -rw-r--r-- | board/vamrs/rock960_rk3399/rock960-rk3399.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 68a127b9ac1..a7fc38d42f8 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,3 +2,27 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ + +#include <common.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <linux/bitops.h> + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /** + * Some SSD's to work on rock960 would require explicit + * domain voltage change, so BT565 is in 1.8v domain + */ + rk_setreg(&grf->io_vsel, BIT(0)); + + return 0; +} +#endif |