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authorTom Rini2022-09-26 11:28:14 -0400
committerTom Rini2022-09-26 11:28:14 -0400
commit55ccdee3155c6cc30eeee846879d06aba6e3fabe (patch)
tree4cda01be7fa0553410ffc193f4f931910efbbf57 /board/xilinx
parentffa2c88bcf8618b6d6fb71f5263beede9a179b20 (diff)
parentf2641f066b53a2bbb933bccffd696a875fd9adf5 (diff)
Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
Diffstat (limited to 'board/xilinx')
-rw-r--r--board/xilinx/Kconfig6
-rw-r--r--board/xilinx/versal-net/Kconfig9
-rw-r--r--board/xilinx/versal-net/MAINTAINERS8
-rw-r--r--board/xilinx/versal-net/Makefile9
-rw-r--r--board/xilinx/versal-net/board.c170
5 files changed, 199 insertions, 3 deletions
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 17880661736..746a2332ad5 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -42,7 +42,7 @@ endif
config XILINX_OF_BOARD_DTB_ADDR
hex "Default DTB pickup address"
- default 0x1000 if ARCH_VERSAL
+ default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET
default 0x8000 if MICROBLAZE
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
depends on OF_BOARD || OF_SEPARATE
@@ -51,10 +51,10 @@ config XILINX_OF_BOARD_DTB_ADDR
config BOOT_SCRIPT_OFFSET
hex "Boot script offset"
- depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || MICROBLAZE
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE
default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
default 0x3E80000 if ARCH_ZYNQMP
- default 0x7F80000 if ARCH_VERSAL
+ default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
help
Specifies distro boot script offset in NAND/QSPI/NOR flash.
diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig
new file mode 100644
index 00000000000..8f94d2bb399
--- /dev/null
+++ b/board/xilinx/versal-net/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2020 - 2022, Xilinx, Inc.
+# Copyright (C) 2022, Advanced Micro Devices, Inc.
+#
+
+if ARCH_VERSAL_NET
+
+endif
diff --git a/board/xilinx/versal-net/MAINTAINERS b/board/xilinx/versal-net/MAINTAINERS
new file mode 100644
index 00000000000..50120a88d6e
--- /dev/null
+++ b/board/xilinx/versal-net/MAINTAINERS
@@ -0,0 +1,8 @@
+XILINX_VERSAL_NET BOARDS
+M: Michal Simek <michal.simek@amd.com>
+S: Maintained
+T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+F: arch/arm/dts/versal-net*
+F: board/xilinx/versal-net/
+F: include/configs/xilinx_versal_net*
+F: configs/xilinx_versal_net*
diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile
new file mode 100644
index 00000000000..2008d4e231c
--- /dev/null
+++ b/board/xilinx/versal-net/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2021 - 2022, Xilinx, Inc.
+# Copyright (C) 2022, Advanced Micro Devices, Inc.
+#
+# Michal Simek <michal.simek@amd.com>
+#
+
+obj-y := board.o
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
new file mode 100644
index 00000000000..760031927f7
--- /dev/null
+++ b/board/xilinx/versal-net/board.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include "../common/board.h"
+
+#include <linux/bitfield.h>
+#include <debug_uart.h>
+#include <generated/dt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ printf("EL Level:\tEL%d\n", current_el());
+
+ return 0;
+}
+
+static u32 platform_id, platform_version;
+
+char *soc_name_decode(void)
+{
+ char *name, *platform_name;
+
+ switch (platform_id) {
+ case VERSAL_NET_SPP:
+ platform_name = "ipp";
+ break;
+ case VERSAL_NET_EMU:
+ platform_name = "emu";
+ break;
+ case VERSAL_NET_QEMU:
+ platform_name = "qemu";
+ break;
+ default:
+ return NULL;
+ }
+
+ /*
+ * --rev. are 6 chars
+ * max platform name is qemu which is 4 chars
+ * platform version number are 1+1
+ * Plus 1 char for \n
+ */
+ name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
+ if (!name)
+ return NULL;
+
+ sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD,
+ platform_name, platform_version / 10,
+ platform_version % 10);
+
+ return name;
+}
+
+bool soc_detection(void)
+{
+ u32 version;
+
+ version = readl(PMC_TAP_VERSION);
+ platform_id = FIELD_GET(PLATFORM_MASK, version);
+
+ debug("idcode %x, version %x, usercode %x\n",
+ readl(PMC_TAP_IDCODE), version,
+ readl(PMC_TAP_USERCODE));
+
+ debug("pmc_ver %lx, ps version %lx, rtl version %lx\n",
+ FIELD_GET(PMC_VERSION_MASK, version),
+ FIELD_GET(PS_VERSION_MASK, version),
+ FIELD_GET(RTL_VERSION_MASK, version));
+
+ platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
+
+ if (platform_id == VERSAL_NET_SPP ||
+ platform_id == VERSAL_NET_EMU) {
+ /*
+ * 9 is diff for
+ * 0 means 0.9 version
+ * 1 means 1.0 version
+ * 2 means 1.1 version
+ * etc,
+ */
+ platform_version += 9;
+ }
+
+ debug("Platform id: %d version: %d.%d\n", platform_id,
+ platform_version / 10, platform_version % 10);
+
+ return true;
+}
+
+int board_early_init_f(void)
+{
+ if (IS_ENABLED(CONFIG_DEBUG_UART)) {
+ /* Uart debug for sure */
+ debug_uart_init();
+ puts("Debug uart enabled\n"); /* or printch() */
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
+
+ if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+ return 0;
+
+ return board_late_init_xilinx();
+}
+
+int dram_init_banksize(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ mem_map_fill();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ if (CONFIG_IS_ENABLED(SYS_MEM_RSVD_FOR_MMU))
+ ret = fdtdec_setup_mem_size_base();
+ else
+ ret = fdtdec_setup_mem_size_base_lowest();
+
+ if (ret)
+ return -EINVAL;
+
+ return 0;
+}
+
+void reset_cpu(void)
+{
+}