arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet

The Zyxel NSA310s board has the network chip Marvell Alaska 88E1318S.
Use uclass mvgbe and the compatible driver M88E1310 driver to bring
up Ethernet.

- Use uclass mvgbe to bring up the network. And remove ad-hoc code.
- Remove CONFIG_RESET_PHY_R.
- Enable CONFIG_PHY_MARVELL to properly configure the network.
- Add phy mode RGMII to kirkwood-nsa310s.dts
- Miscellaneous changes: Move constants to .c file and remove header file
board/zyxel/nsa310s/nsa310s.h, add support for large USB and SATA HDDs,
use BIT macro, add/cleanup comments, and cosmetic changes.

Note that this patch is depended on the following patch:
https://patchwork.ozlabs.org/project/uboot/patch/20220412201820.10291-1-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>

1 files changed, 33 insertions, 86 deletions

diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
index b71de4e11f0..b3ea6608914 100644
--- a/board/zyxel/nsa310s/nsa310s.c
+++ b/board/zyxel/nsa310s/nsa310s.c
@@ -1,22 +1,49 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
  * Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
  */
 
 #include <common.h>
 #include <init.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
-#include "nsa310s.h"
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * low GPIO's
+ */
+#define HDD1_GREEN_LED		BIT(16)
+#define HDD1_RED_LED		BIT(13)
+#define USB_GREEN_LED		BIT(15)
+#define USB_POWER		BIT(21)
+#define SYS_GREEN_LED		BIT(28)
+#define SYS_ORANGE_LED		BIT(29)
+
+#define COPY_GREEN_LED		BIT(22)
+#define COPY_RED_LED		BIT(23)
+
+#define PIN_USB_GREEN_LED	15
+#define PIN_USB_POWER		21
+
+#define NSA310S_OE_LOW		(~(0))
+#define NSA310S_VAL_LOW		(SYS_GREEN_LED | USB_POWER)
+
+/*
+ * high GPIO's
+ */
+#define HDD2_GREEN_LED		BIT(2)
+#define HDD2_POWER		BIT(1)
+
+#define NSA310S_OE_HIGH		(~(0))
+#define NSA310S_VAL_HIGH	(HDD2_POWER)
+
 int board_early_init_f(void)
 {
 	/*
@@ -80,87 +107,7 @@ int board_init(void)
 	return 0;
 }
 
-static int fdt_get_phy_addr(const char *path)
-{
-	const void *fdt = gd->fdt_blob;
-	const u32 *reg;
-	const u32 *val;
-	int node, phandle, addr;
-
-	/* Find the node by its full path */
-	node = fdt_path_offset(fdt, path);
-	if (node >= 0) {
-		/* Look up phy-handle */
-		val = fdt_getprop(fdt, node, "phy-handle", NULL);
-		if (val) {
-			phandle = fdt32_to_cpu(*val);
-			if (!phandle)
-				return -1;
-			/* Follow it to its node */
-			node = fdt_node_offset_by_phandle(fdt, phandle);
-			if (node) {
-				/* Look up reg */
-				reg = fdt_getprop(fdt, node, "reg", NULL);
-				if (reg) {
-					addr = fdt32_to_cpu(*reg);
-					return addr;
-				}
-			}
-		}
-	}
-	return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
+int board_eth_init(struct bd_info *bis)
 {
-	u16 reg;
-	u16 phyaddr;
-	char *name = "ethernet-controller@72000";
-	char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	phyaddr = fdt_get_phy_addr(eth0_path);
-	if (phyaddr < 0)
-		return;
-
-	/* set RGMII delay */
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
-	miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
-	reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
-	miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
-	/* reset PHY */
-	if (miiphy_reset(name, phyaddr))
-		return;
-
-	/*
-	 * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
-	 * and has an MCU attached to the LED[2] via tristate interrupt
-	 */
-
-	/* switch to LED register page */
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
-	/* read out LED polarity register */
-	miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg);
-	/* clear 4, set 5 - LED2 low, tri-state */
-	reg &= ~(MV88E1318_LED2_4);
-	reg |= (MV88E1318_LED2_5);
-	/* write back LED polarity register */
-	miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
-	/* jump back to page 0, per the PHY chip documenation. */
-	miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
-	/* set PHY back to auto-negotiation mode */
-	miiphy_write(name, phyaddr, 0x4, 0x1e1);
-	miiphy_write(name, phyaddr, 0x9, 0x300);
-	/* downshift */
-	miiphy_write(name, phyaddr, 0x10, 0x3860);
-	miiphy_write(name, phyaddr, 0x0, 0x9140);
-
-	printf("MV88E1318 PHY initialized on %s\n", name);
+	return cpu_eth_init(bis);
 }
-#endif /* CONFIG_RESET_PHY_R */