Merge branch 'next'

40 files changed, 612 insertions, 151 deletions

diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
index 7df37e4e66a..c8dc186cddf 100644
--- a/board/BuR/brppt1/board.c
+++ b/board/BuR/brppt1/board.c
@@ -151,9 +151,7 @@ int board_init(void)
 	hw_watchdog_init();
 #endif
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_MTD_RAW_NAND
-	gpmc_init();
-#endif
+
 	return 0;
 }
 
diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c
index b863d373350..5d2c7a201ea 100644
--- a/board/BuR/brppt1/mux.c
+++ b/board/BuR/brppt1/mux.c
@@ -26,6 +26,7 @@ static struct module_pin_mux uart0_pin_mux[] = {
 	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
 	{-1},
 };
+
 static struct module_pin_mux uart1_pin_mux[] = {
 	/* UART1_RTS as I2C2-SCL */
 	{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
@@ -37,7 +38,7 @@ static struct module_pin_mux uart1_pin_mux[] = {
 	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
 	{-1},
 };
-#ifdef CONFIG_MMC
+
 static struct module_pin_mux mmc1_pin_mux[] = {
 	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
 	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
@@ -54,7 +55,7 @@ static struct module_pin_mux mmc1_pin_mux[] = {
 	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
 	{-1},
 };
-#endif
+
 static struct module_pin_mux i2c0_pin_mux[] = {
 	/* I2C_DATA */
 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
@@ -118,26 +119,7 @@ static struct module_pin_mux mii2_pin_mux[] = {
 	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
 	{-1},
 };
-#ifdef CONFIG_MTD_RAW_NAND
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-#endif
+
 static struct module_pin_mux gpIOs[] = {
 	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
 	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
@@ -180,14 +162,6 @@ static struct module_pin_mux gpIOs[] = {
 	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
 	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
 	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
-#ifndef CONFIG_MTD_RAW_NAND
-	/* GPIO2_3 - NAND_OE */
-	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-	/* GPIO2_4 - NAND_WEN */
-	{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-	/* GPIO2_5 - NAND_BE_CLE */
-	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-#endif
 	{-1},
 };
 
@@ -222,7 +196,6 @@ static struct module_pin_mux lcd_pin_mux[] = {
 	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
 	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
 	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
-
 	{-1},
 };
 
@@ -241,11 +214,7 @@ void enable_board_pin_mux(void)
 	configure_module_pin_mux(i2c0_pin_mux);
 	configure_module_pin_mux(mii1_pin_mux);
 	configure_module_pin_mux(mii2_pin_mux);
-#ifdef CONFIG_MTD_RAW_NAND
-	configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_MMC)
 	configure_module_pin_mux(mmc1_pin_mux);
-#endif
 	configure_module_pin_mux(spi0_pin_mux);
 	configure_module_pin_mux(lcd_pin_mux);
 	configure_module_pin_mux(uart1_pin_mux);
diff --git a/board/Marvell/octeon_nic23/board.c b/board/Marvell/octeon_nic23/board.c
index 3e2c5444439..08b1aa4b6ef 100644
--- a/board/Marvell/octeon_nic23/board.c
+++ b/board/Marvell/octeon_nic23/board.c
@@ -3,8 +3,10 @@
  * Copyright (C) 2021-2022 Stefan Roese <sr@denx.de>
  */
 
+#include <cyclic.h>
 #include <dm.h>
 #include <ram.h>
+#include <time.h>
 #include <asm/gpio.h>
 
 #include <mach/octeon_ddr.h>
@@ -15,11 +17,90 @@
 #include <mach/cvmx-helper-cfg.h>
 #include <mach/cvmx-helper-util.h>
 #include <mach/cvmx-bgxx-defs.h>
+#include <mach/cvmx-dtx-defs.h>
 
 #include "board_ddr.h"
 
+/**
+ * cvmx_spem#_cfg_rd
+ *
+ * This register allows read access to the configuration in the PCIe core.
+ *
+ */
+union cvmx_spemx_cfg_rd {
+	u64 u64;
+	struct cvmx_spemx_cfg_rd_s {
+		u64 data                         : 32;
+		u64 addr                         : 32;
+	} s;
+	struct cvmx_spemx_cfg_rd_s            cn73xx;
+};
+
+/**
+ * cvmx_spem#_cfg_wr
+ *
+ * This register allows write access to the configuration in the PCIe core.
+ *
+ */
+union cvmx_spemx_cfg_wr {
+	u64 u64;
+	struct cvmx_spemx_cfg_wr_s {
+		u64 data                         : 32;
+		u64 addr                         : 32;
+	} s;
+	struct cvmx_spemx_cfg_wr_s            cn73xx;
+};
+
+/**
+ * cvmx_spem#_flr_pf_stopreq
+ *
+ * PF function level reset stop outbound requests register.
+ * Hardware automatically sets the STOPREQ bit for the PF when it enters a
+ * function level reset (FLR).  Software is responsible for clearing the STOPREQ
+ * bit but must not do so prior to hardware taking down the FLR, which could be
+ * as long as 100ms.  It may be appropriate for software to wait longer before clearing
+ * STOPREQ, software may need to drain deep DPI queues for example.
+ * Whenever SPEM receives a PF or child VF request mastered by CNXXXX over S2M (i.e. P or NP),
+ * when STOPREQ is set for the function, SPEM will discard the outgoing request
+ * before sending it to the PCIe core.  If a NP, SPEM will schedule an immediate
+ * SWI_RSP_ERROR completion for the request - no timeout is required.
+ * In both cases, SPEM()_DBG_PF()_INFO[P()_BMD_E] will be set and a error
+ * interrupt is generated.
+ *
+ * STOPREQ mimics the behavior of PCIEEP()_CFG001[ME] for outbound requests that will
+ * master the PCIe bus (P and NP).
+ *
+ * STOPREQ will have no effect on completions returned by CNXXXX over the S2M,
+ * nor on M2S traffic.
+ *
+ * When a PF()_STOPREQ is set, none of the associated
+ * PEM()_FLR_PF()_VF_STOPREQ[VF_STOPREQ] will be set.
+ *
+ * STOPREQ is reset when the MAC is reset, and is not reset after a chip soft reset.
+ */
+union cvmx_spemx_flr_pf_stopreq {
+	u64 u64;
+	struct cvmx_spemx_flr_pf_stopreq_s {
+		u64 reserved_3_63                : 61;
+		u64 pf2_stopreq                  : 1;
+		u64 pf1_stopreq                  : 1;
+		u64 pf0_stopreq                  : 1;
+	} s;
+	struct cvmx_spemx_flr_pf_stopreq_s    cn73xx;
+};
+
+#define CVMX_SPEMX_CFG_WR(offset)		0x00011800C0000028ull
+#define CVMX_SPEMX_CFG_RD(offset)		0x00011800C0000030ull
+#define CVMX_SPEMX_FLR_PF_STOPREQ(offset)	0x00011800C0000218ull
+
+#define DTX_SELECT_LTSSM		0x0
+#define DTX_SELECT_LTSSM_ENA		0x3ff
+#define LTSSM_L0			0x11
+
 #define NIC23_DEF_DRAM_FREQ		800
 
+static u32 pci_cfgspace_reg0[2] = { 0, 0 };
+
 static u8 octeon_nic23_cfg0_spd_values[512] = {
 	OCTEON_NIC23_CFG0_SPD_VALUES
 };
@@ -145,8 +226,118 @@ void board_configure_qlms(void)
 	      cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5));
 }
 
+/**
+ * If there is a PF FLR then the PCI EEPROM is not re-read.  In this case
+ * we need to re-program the vendor and device ID immediately after hardware
+ * completes FLR.
+ *
+ * PCI spec requires FLR to be completed within 100ms.  The user who triggered
+ * FLR expects hardware to finish FLR within 100ms, otherwise the user will
+ * end up reading DEVICE_ID incorrectly from the reset value.
+ * CN23XX exits FLR at any point between 66 and 99ms, so U-Boot has to wait
+ * 99ms to let hardware finish its part, then finish reprogramming the
+ * correct device ID before the end of 100ms.
+ *
+ * Note: this solution only works properly when there is no other activity
+ * within U-Boot for 100ms from the time FLR is triggered.
+ *
+ * This function gets called every 100usec.  If FLR happens during any
+ * other activity like bootloader/image update then it is possible that
+ * this function does not get called for more than the FLR period which will
+ * cause the PF device ID restore to happen after whoever initiated the FLR to
+ * read the incorrect device ID 0x9700 (reset value) instead of 0x9702
+ * (restored value).
+ */
+static void octeon_board_restore_pf(void *ctx)
+{
+	union cvmx_spemx_flr_pf_stopreq stopreq;
+	static bool start_initialized[2] = {false, false};
+	bool pf0_flag, pf1_flag;
+	u64 ltssm_bits;
+	const u64 pf_flr_wait_usecs = 99700;
+	u64 elapsed_usecs;
+	union cvmx_spemx_cfg_wr cfg_wr;
+	union cvmx_spemx_cfg_rd cfg_rd;
+	static u64 start_us[2];
+	int pf_num;
+
+	csr_wr(CVMX_DTX_SPEM_SELX(0), DTX_SELECT_LTSSM);
+	csr_rd(CVMX_DTX_SPEM_SELX(0));
+	csr_wr(CVMX_DTX_SPEM_ENAX(0), DTX_SELECT_LTSSM_ENA);
+	csr_rd(CVMX_DTX_SPEM_ENAX(0));
+	ltssm_bits = csr_rd(CVMX_DTX_SPEM_DATX(0));
+	if (((ltssm_bits >> 3) & 0x3f) != LTSSM_L0)
+		return;
+
+	stopreq.u64 = csr_rd(CVMX_SPEMX_FLR_PF_STOPREQ(0));
+	pf0_flag = stopreq.s.pf0_stopreq;
+	pf1_flag = stopreq.s.pf1_stopreq;
+	/* See if PF interrupt happened */
+	if (!(pf0_flag || pf1_flag))
+		return;
+
+	if (pf0_flag && !start_initialized[0]) {
+		start_initialized[0] = true;
+		start_us[0] = get_timer_us(0);
+	}
+
+	/* Store programmed PCIe DevID SPEM0 PF0 */
+	if (pf0_flag && !pci_cfgspace_reg0[0]) {
+		cfg_rd.s.addr = (0 << 24) | 0x0;
+		csr_wr(CVMX_SPEMX_CFG_RD(0), cfg_rd.u64);
+		cfg_rd.u64 = csr_rd(CVMX_SPEMX_CFG_RD(0));
+		pci_cfgspace_reg0[0] = cfg_rd.s.data;
+	}
+
+	if (pf1_flag && !start_initialized[1]) {
+		start_initialized[1] = true;
+		start_us[1] = get_timer_us(0);
+	}
+
+	/* Store programmed PCIe DevID SPEM0 PF1 */
+	if (pf1_flag && !pci_cfgspace_reg0[1]) {
+		cfg_rd.s.addr = (1 << 24) | 0x0;
+		csr_wr(CVMX_SPEMX_CFG_RD(0), cfg_rd.u64);
+		cfg_rd.u64 = csr_rd(CVMX_SPEMX_CFG_RD(0));
+		pci_cfgspace_reg0[1] = cfg_rd.s.data;
+	}
+
+	/* For PF, rewrite pci config space reg 0 */
+	for (pf_num = 0; pf_num < 2; pf_num++) {
+		if (!start_initialized[pf_num])
+			continue;
+
+		elapsed_usecs = get_timer_us(0) - start_us[pf_num];
+
+		if (elapsed_usecs > pf_flr_wait_usecs) {
+			/* Here, our measured FLR duration has passed;
+			 * check if device ID has been reset,
+			 * which indicates FLR completion (per MA team).
+			 */
+			cfg_rd.s.addr = (pf_num << 24) | 0x0;
+			csr_wr(CVMX_SPEMX_CFG_RD(0), cfg_rd.u64);
+			cfg_rd.u64 = csr_rd(CVMX_SPEMX_CFG_RD(0));
+			/* if DevID has NOT been reset, FLR is not yet
+			 * complete
+			 */
+			if (cfg_rd.s.data != pci_cfgspace_reg0[pf_num]) {
+				stopreq.s.pf0_stopreq = (pf_num == 0) ? 1 : 0;
+				stopreq.s.pf1_stopreq = (pf_num == 1) ? 1 : 0;
+				csr_wr(CVMX_SPEMX_FLR_PF_STOPREQ(0), stopreq.u64);
+
+				cfg_wr.u64 = 0;
+				cfg_wr.s.addr = (pf_num << 24) | 0;
+				cfg_wr.s.data = pci_cfgspace_reg0[pf_num];
+				csr_wr(CVMX_SPEMX_CFG_WR(0), cfg_wr.u64);
+				start_initialized[pf_num] = false;
+			}
+		}
+	}
+}
+
 int board_late_init(void)
 {
+	struct cyclic_info *cyclic;
 	struct gpio_desc gpio = {};
 	ofnode node;
 
@@ -164,6 +355,12 @@ int board_late_init(void)
 
 	board_configure_qlms();
 
+	/* Register cyclic function for PCIe FLR fixup */
+	cyclic = cyclic_register(octeon_board_restore_pf, 100,
+				 "pcie_flr_fix", NULL);
+	if (!cyclic)
+		printf("Registering of cyclic function failed\n");
+
 	return 0;
 }
 
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 50a3830b857..f85737432b3 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -123,7 +123,7 @@ int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
 
 		if (bytecount % len_40 == 0) {
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
-			WATCHDOG_RESET();
+			schedule();
 #endif
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			putc('.');	/* let them know we are alive */
@@ -343,7 +343,7 @@ int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
 		}
 		if (bytecount % len_40 == 0) {
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
-			WATCHDOG_RESET();
+			schedule();
 #endif
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 			putc('.');	/* let them know we are alive */
diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
index d8f32c93b55..8cf67d148dd 100644
--- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
+++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
@@ -19,6 +19,8 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
+extern void at91_pda_detect(void);
+
 DECLARE_GLOBAL_DATA_PTR;
 
 void at91_prepare_cpu_var(void);
@@ -27,6 +29,8 @@ int board_late_init(void)
 {
 	at91_prepare_cpu_var();
 
+	at91_pda_detect();
+
 	return 0;
 }
 
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c
index 88036c16c95..26652e8f773 100644
--- a/board/broadcom/bcmns3/ns3.c
+++ b/board/broadcom/bcmns3/ns3.c
@@ -183,7 +183,7 @@ int dram_init_banksize(void)
 }
 
 /* Limit RAM used by U-Boot to the DDR first bank End region */
-ulong board_get_usable_ram_top(ulong total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	return BCM_NS3_MEM_END;
 }
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index e49e97724a5..20a330cce62 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <init.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/crm_regs.h>
@@ -14,11 +15,13 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
+#include <asm/system.h>
 #include <errno.h>
 #include <fuse.h>
 #include <fsl_esdhc_imx.h>
@@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void)
 	}
 }
 
+void dram_bank_mmu_setup(int bank)
+{
+	int i;
+
+	set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
+	set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
+
+	for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
+			i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +
+			(SZ_1G >> MMU_SECTION_SHIFT));
+			i++)
+		set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
+
 void board_init_f(ulong dummy)
 {
 	/* setup AIPS and disable watchdog */
@@ -636,9 +653,33 @@ void board_init_f(ulong dummy)
 	/* DDR3 initialization */
 	dhcom_spl_dram_init();
 
+	/* Set up early MMU tables at the beginning of DRAM and start d-cache */
+	gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	enable_caches();
+
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
+
+void spl_board_prepare_for_boot(void)
+{
+	/*
+	 * Flush and disable dcache. Without it, the following bootstage might fail randomly because
+	 * dirty cache lines may not have been written back to DRAM.
+	 *
+	 * If dcache_disable() would be omitted, the following scenario may occur:
+	 *
+	 * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled
+	 * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations
+	 * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old
+	 * state of the content.
+	 *
+	 * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was
+	 * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data.
+	 */
+	dcache_disable(); /* implies flush_dcache_all() */
+}
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 9188f5381eb..2bc0d7b943a 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -423,7 +423,7 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
 		for (i = 0; i < 2 * nb_blink; i++) {
 			led_set_state(led, LEDST_TOGGLE);
 			mdelay(125);
-			WATCHDOG_RESET();
+			schedule();
 		}
 	}
 #endif
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index 182f79b9182..5b245cb4473 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c
@@ -23,7 +23,7 @@ int dram_init(void)
 	return 0;
 }
 
-ulong board_get_usable_ram_top(ulong total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
index 5c1af1a7720..4219d002fec 100644
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@@ -329,7 +329,7 @@ void board_init_f(ulong dummy)
 	/* Initialize and reset WDT in SPL */
 #ifdef CONFIG_SPL_WATCHDOG
 	hw_watchdog_init();
-	WATCHDOG_RESET();
+	schedule();
 #endif
 
 	/* load/boot image from boot device */
diff --git a/board/mediatek/mt7981/MAINTAINERS b/board/mediatek/mt7981/MAINTAINERS
new file mode 100644
index 00000000000..e7592a7a548
--- /dev/null
+++ b/board/mediatek/mt7981/MAINTAINERS
@@ -0,0 +1,10 @@
+MT7981
+M:	Sam Shih <sam.shih@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7981
+F:	include/configs/mt7981.h
+F:	configs/mt7981_emmc_rfb_defconfig
+F:	configs/mt7981_rfb_defconfig
+F:	configs/mt7981_sd_rfb_defconfig
+F:	configs/mt7981_spim_nand_rfb_defconfig
+F:	configs/mt7981_spim_nor_rfb_defconfig
diff --git a/board/mediatek/mt7981/Makefile b/board/mediatek/mt7981/Makefile
new file mode 100644
index 00000000000..fa5990ffb2c
--- /dev/null
+++ b/board/mediatek/mt7981/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= mt7981_rfb.o
diff --git a/board/mediatek/mt7981/mt7981_rfb.c b/board/mediatek/mt7981/mt7981_rfb.c
new file mode 100644
index 00000000000..846c715ca05
--- /dev/null
+++ b/board/mediatek/mt7981/mt7981_rfb.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/mediatek/mt7986/MAINTAINERS b/board/mediatek/mt7986/MAINTAINERS
new file mode 100644
index 00000000000..ddc078a567a
--- /dev/null
+++ b/board/mediatek/mt7986/MAINTAINERS
@@ -0,0 +1,12 @@
+MT7986
+M:	Sam Shih <sam.shih@mediatek.com>
+S:	Maintained
+F:	board/mediatek/mt7986
+F:	include/configs/mt7986.h
+F:	configs/mt7986_rfb_defconfig
+F:	configs/mt7986a_bpir3_emmc_defconfig
+F:	configs/mt7986a_bpir3_sd_defconfig
+F:	configs/mt7986a_emmc_rfb_defconfig
+F:	configs/mt7986a_sd_rfb_defconfig
+F:	configs/mt7986b_emmc_rfb_defconfig
+F:	configs/mt7986b_sd_rfb_defconfig
diff --git a/board/mediatek/mt7986/Makefile b/board/mediatek/mt7986/Makefile
new file mode 100644
index 00000000000..7bb84fa2f4e
--- /dev/null
+++ b/board/mediatek/mt7986/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= mt7986_rfb.o
diff --git a/board/mediatek/mt7986/mt7986_rfb.c b/board/mediatek/mt7986/mt7986_rfb.c
new file mode 100644
index 00000000000..846c715ca05
--- /dev/null
+++ b/board/mediatek/mt7986/mt7986_rfb.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 61ab3844b87..4afc5aaa436 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static u32 mx53_dram_size[2];
 
-ulong board_get_usable_ram_top(ulong total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	/*
 	 * WARNING: We must override get_effective_memsize() function here
diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S
index c1785bc3f72..1cf8f8d8b2f 100644
--- a/board/nokia/rx51/lowlevel_init.S
+++ b/board/nokia/rx51/lowlevel_init.S
@@ -46,7 +46,6 @@ save_boot_params:
  * (CONFIG_SYS_TEXT_BASE).
  */
 
-copy_kernel_start:
 	/* r0 - start of kernel before */
 	adr	r0, kernoffs	/* r0 - current address of kernoffs section */
 	ldr	r1, kernoffs	/* r1 - offset of kernel image from kernoffs section */
@@ -77,7 +76,7 @@ copy_kernel_start:
 	ldr	r4, [r0, #36]	/* r4 - 4 bytes header of kernel at offset 36 */
 	ldr	r5, z_magic	/* r5 - LINUX_ARM_ZIMAGE_MAGIC */
 	cmp	r4, r5
-	bne	copy_kernel_end	/* skip if invalid image */
+	bne	skip_copy	/* skip if invalid image */
 
 copy_kernel_loop:
 	ldmdb	r1!, {r3 - r10}
@@ -85,12 +84,12 @@ copy_kernel_loop:
 	cmp	r1, r0
 	bhi	copy_kernel_loop
 
-copy_kernel_end:
-
 	/* remove header in source kernel image */
 	mov	r5, #0
 	str	r5, [r0]	/* remove 4 bytes header of kernel uImage */
 	str	r5, [r0, #36]	/* remove 4 bytes header of kernel zImage */
 
+skip_copy:
+
 	/* Returns */
 	b	save_boot_params_ret
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 460d248eaae..9548c3c7be7 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -722,7 +722,7 @@ static int rx51_kp_getc(struct udevice *dev)
 {
 	keybuf_head %= KEYBUF_SIZE;
 	while (!rx51_kp_tstc(dev))
-		WATCHDOG_RESET();
+		schedule();
 	return keybuf[keybuf_head++];
 }
 
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
index f1e6e7f7eb5..249dca7e72f 100644
--- a/board/qualcomm/qcs404-evb/qcs404-evb.c
+++ b/board/qualcomm/qcs404-evb/qcs404-evb.c
@@ -11,6 +11,7 @@
 #include <env.h>
 #include <init.h>
 #include <asm/cache.h>
+#include <asm/gpio.h>
 #include <asm/global_data.h>
 #include <fdt_support.h>
 #include <asm/arch/dram.h>
@@ -24,6 +25,34 @@ int dram_init(void)
 
 int board_init(void)
 {
+	struct udevice *pmic_gpio;
+	struct gpio_desc usb_vbus_boost_pin;
+	int ret, node;
+
+	ret = uclass_get_device_by_name(UCLASS_GPIO,
+					"pms405_gpios@c000",
+					&pmic_gpio);
+	if (ret < 0) {
+		printf("Failed to find pms405_gpios@c000 node.\n");
+		return ret;
+	}
+
+	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
+				  "usb_vbus_boost_pin");
+	if (node < 0) {
+		printf("Failed to find usb_hub_reset_pm dt node.\n");
+		return node;
+	}
+	ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+					 &usb_vbus_boost_pin, 0);
+	if (ret < 0) {
+		printf("Failed to request usb_hub_reset_pm gpio.\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
+			      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
 	return 0;
 }
 
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 17b8108cc88..00afb352bd1 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -335,7 +335,7 @@ static void set_fdt_addr(void)
 /*
  * Prevent relocation from stomping on a firmware provided FDT blob.
  */
-unsigned long board_get_usable_ram_top(unsigned long total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
 		return gd->ram_top;
diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c
index fa48b2a35ee..0096f71dfc1 100644
--- a/board/st/common/stm32mp_dfu.c
+++ b/board/st/common/stm32mp_dfu.c
@@ -37,7 +37,7 @@ static void board_get_alt_info_mmc(struct udevice *dev, char *buf)
 	if (!desc)
 		return;
 
-	name = blk_get_if_type_name(desc->if_type);
+	name = blk_get_uclass_name(desc->uclass_id);
 	devnum = desc->devnum;
 	len = strlen(buf);
 
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 8c162b42a59..2d98ff41abf 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -289,7 +289,7 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
 			for (i = 0; i < 2 * nb_blink; i++) {
 				led_set_state(led, LEDST_TOGGLE);
 				mdelay(125);
-				WATCHDOG_RESET();
+				schedule();
 			}
 			led_set_state(led, LEDST_ON);
 		}
@@ -898,8 +898,8 @@ int mmc_get_env_dev(void)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	static const struct node_info nodes[] = {
-		{ "st,stm32f469-qspi",		MTD_DEV_TYPE_NOR,  },
-		{ "st,stm32f469-qspi",		MTD_DEV_TYPE_SPINAND},
+		{ "jedec,spi-nor",		MTD_DEV_TYPE_NOR,  },
+		{ "spi-nand",			MTD_DEV_TYPE_SPINAND},
 		{ "st,stm32mp15-fmc2",		MTD_DEV_TYPE_NAND, },
 		{ "st,stm32mp1-fmc2-nfc",	MTD_DEV_TYPE_NAND, },
 	};
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 226fbba6296..4308c7e440a 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -844,7 +844,7 @@ static int hsdk_go_run(u32 cpu_start_reg)
 	return 0;
 }
 
-int board_prep_linux(bootm_headers_t *images)
+int board_prep_linux(struct bootm_headers *images)
 {
 	int ret, ofst;
 	char mask[15];
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 8a0a506a3e3..34ec3915f3d 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -61,7 +61,7 @@ int dram_init(void)
 	return 0;
 }
 
-ulong board_get_usable_ram_top(ulong total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_PHYS_64BIT
 	/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 5d090048ceb..d6e431ead0e 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -57,7 +57,7 @@ int dram_init(void)
 	return 0;
 }
 
-ulong board_get_usable_ram_top(ulong total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_PHYS_64BIT
 	/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 3c75ecfc0fe..e09adc8ad34 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -46,7 +46,7 @@ int dram_init(void)
 	return 0;
 }
 
-ulong board_get_usable_ram_top(ulong total_size)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 {
 #ifdef CONFIG_PHYS_64BIT
 	/* Limit RAM used by U-Boot to the DDR low region */
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 0c5c2c9146f..5ba3aa35a9f 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -64,9 +64,9 @@ int dram_init(void)
 	return 0;
 }
 
-struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
 {
-	return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+	return (struct legacy_img_hdr *)(CONFIG_SYS_TEXT_BASE);
 }
 
 int board_init(void)
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 22c67c6e388..11f4d5e14a8 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -211,7 +211,7 @@ static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
 		return -EINVAL;
 	}
 	if (part != mmc_get_blk_desc(mmc)->hwpart) {
-		if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
+		if (blk_select_hwpart_devnum(UCLASS_MMC, dev, part)) {
 			puts("MMC partition switch failed\n");
 			ret = -ENODEV;
 			goto out;
@@ -239,7 +239,7 @@ static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
 
 out:
 	/* Switch back to regular eMMC user partition */
-	blk_select_hwpart_devnum(IF_TYPE_MMC, 0, 0);
+	blk_select_hwpart_devnum(UCLASS_MMC, 0, 0);
 
 	return ret;
 }
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 17880661736..746a2332ad5 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -42,7 +42,7 @@ endif
 
 config XILINX_OF_BOARD_DTB_ADDR
 	hex "Default DTB pickup address"
-	default 0x1000 if ARCH_VERSAL
+	default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET
 	default 0x8000 if MICROBLAZE
 	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
 	depends on OF_BOARD || OF_SEPARATE
@@ -51,10 +51,10 @@ config XILINX_OF_BOARD_DTB_ADDR
 
 config BOOT_SCRIPT_OFFSET
 	hex "Boot script offset"
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || MICROBLAZE
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE
 	default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
 	default 0x3E80000 if ARCH_ZYNQMP
-	default 0x7F80000 if ARCH_VERSAL
+	default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
 	help
 	   Specifies distro boot script offset in NAND/QSPI/NOR flash.
 
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 9b4aded466a..391ce4dbd72 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -8,6 +8,8 @@
 #include <efi.h>
 #include <efi_loader.h>
 #include <env.h>
+#include <image.h>
+#include <lmb.h>
 #include <log.h>
 #include <asm/global_data.h>
 #include <asm/sections.h>
@@ -583,8 +585,33 @@ bool __maybe_unused __weak board_detection(void)
 	return false;
 }
 
+bool __maybe_unused __weak soc_detection(void)
+{
+	return false;
+}
+
+char * __maybe_unused __weak soc_name_decode(void)
+{
+	return NULL;
+}
+
 int embedded_dtb_select(void)
 {
+	if (soc_detection()) {
+		char *soc_local_name;
+
+		soc_local_name = soc_name_decode();
+		if (soc_local_name) {
+			board_name = soc_local_name;
+			printf("Detected SOC name: %s\n", board_name);
+
+			/* Time to change DTB on fly */
+			/* Both ways should work here */
+			/* fdtdec_resetup(&rescan); */
+			return fdtdec_setup();
+		}
+	}
+
 	if (board_detection()) {
 		char *board_local_name;
 
@@ -602,3 +629,30 @@ int embedded_dtb_select(void)
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_LMB)
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	phys_size_t size;
+	phys_addr_t reg;
+	struct lmb lmb;
+
+	if (!total_size)
+		return gd->ram_top;
+
+	if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
+		panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
+
+	/* found enough not-reserved memory to relocated U-Boot */
+	lmb_init(&lmb);
+	lmb_add(&lmb, gd->ram_base, gd->ram_size);
+	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
+	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
+	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
+
+	if (!reg)
+		reg = gd->ram_top - size;
+
+	return reg + size;
+}
+#endif
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index f58ecd1590c..a427ac94a17 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -14,8 +14,6 @@
 #include <config.h>
 #include <env.h>
 #include <init.h>
-#include <image.h>
-#include <lmb.h>
 #include <log.h>
 #include <asm/global_data.h>
 #include <dm/lists.h>
@@ -38,25 +36,6 @@ int dram_init(void)
 	return 0;
 };
 
-ulong board_get_usable_ram_top(ulong total_size)
-{
-	phys_size_t size;
-	phys_addr_t reg;
-	struct lmb lmb;
-
-	/* found enough not-reserved memory to relocated U-Boot */
-	lmb_init(&lmb);
-	lmb_add(&lmb, gd->ram_base, gd->ram_size);
-	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
-	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
-	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
-
-	if (!reg)
-		reg = gd->ram_top - size;
-
-	return reg + size;
-}
-
 int board_late_init(void)
 {
 	ulong max_size;
diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig
new file mode 100644
index 00000000000..8f94d2bb399
--- /dev/null
+++ b/board/xilinx/versal-net/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2020 - 2022, Xilinx, Inc.
+# Copyright (C) 2022, Advanced Micro Devices, Inc.
+#
+
+if ARCH_VERSAL_NET
+
+endif
diff --git a/board/xilinx/versal-net/MAINTAINERS b/board/xilinx/versal-net/MAINTAINERS
new file mode 100644
index 00000000000..50120a88d6e
--- /dev/null
+++ b/board/xilinx/versal-net/MAINTAINERS
@@ -0,0 +1,8 @@
+XILINX_VERSAL_NET BOARDS
+M:	Michal Simek <michal.simek@amd.com>
+S:	Maintained
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/versal-net*
+F:	board/xilinx/versal-net/
+F:	include/configs/xilinx_versal_net*
+F:	configs/xilinx_versal_net*
diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile
new file mode 100644
index 00000000000..2008d4e231c
--- /dev/null
+++ b/board/xilinx/versal-net/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2021 - 2022, Xilinx, Inc.
+# Copyright (C) 2022, Advanced Micro Devices, Inc.
+#
+# Michal Simek <michal.simek@amd.com>
+#
+
+obj-y	:= board.o
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
new file mode 100644
index 00000000000..760031927f7
--- /dev/null
+++ b/board/xilinx/versal-net/board.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include "../common/board.h"
+
+#include <linux/bitfield.h>
+#include <debug_uart.h>
+#include <generated/dt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	printf("EL Level:\tEL%d\n", current_el());
+
+	return 0;
+}
+
+static u32 platform_id, platform_version;
+
+char *soc_name_decode(void)
+{
+	char *name, *platform_name;
+
+	switch (platform_id) {
+	case VERSAL_NET_SPP:
+		platform_name = "ipp";
+		break;
+	case VERSAL_NET_EMU:
+		platform_name = "emu";
+		break;
+	case VERSAL_NET_QEMU:
+		platform_name = "qemu";
+		break;
+	default:
+		return NULL;
+	}
+
+	/*
+	 * --rev. are 6 chars
+	 * max platform name is qemu which is 4 chars
+	 * platform version number are 1+1
+	 * Plus 1 char for \n
+	 */
+	name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
+	if (!name)
+		return NULL;
+
+	sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD,
+		platform_name, platform_version / 10,
+		platform_version % 10);
+
+	return name;
+}
+
+bool soc_detection(void)
+{
+	u32 version;
+
+	version = readl(PMC_TAP_VERSION);
+	platform_id = FIELD_GET(PLATFORM_MASK, version);
+
+	debug("idcode %x, version %x, usercode %x\n",
+	      readl(PMC_TAP_IDCODE), version,
+	      readl(PMC_TAP_USERCODE));
+
+	debug("pmc_ver %lx, ps version %lx, rtl version %lx\n",
+	      FIELD_GET(PMC_VERSION_MASK, version),
+	      FIELD_GET(PS_VERSION_MASK, version),
+	      FIELD_GET(RTL_VERSION_MASK, version));
+
+	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
+
+	if (platform_id == VERSAL_NET_SPP ||
+	    platform_id == VERSAL_NET_EMU) {
+		/*
+		 * 9 is diff for
+		 * 0 means 0.9 version
+		 * 1 means 1.0 version
+		 * 2 means 1.1 version
+		 * etc,
+		 */
+		platform_version += 9;
+	}
+
+	debug("Platform id: %d version: %d.%d\n", platform_id,
+	      platform_version / 10, platform_version % 10);
+
+	return true;
+}
+
+int board_early_init_f(void)
+{
+	if (IS_ENABLED(CONFIG_DEBUG_UART)) {
+		/* Uart debug for sure */
+		debug_uart_init();
+		puts("Debug uart enabled\n"); /* or printch() */
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	return board_late_init_xilinx();
+}
+
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int ret;
+
+	if (CONFIG_IS_ENABLED(SYS_MEM_RSVD_FOR_MMU))
+		ret = fdtdec_setup_mem_size_base();
+	else
+		ret = fdtdec_setup_mem_size_base_lowest();
+
+	if (ret)
+		return -EINVAL;
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index d8f39be56c8..f9f5457ed20 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -9,7 +9,6 @@
 #include <env.h>
 #include <fdtdec.h>
 #include <init.h>
-#include <image.h>
 #include <env_internal.h>
 #include <log.h>
 #include <malloc.h>
@@ -270,28 +269,6 @@ int dram_init(void)
 	return 0;
 }
 
-ulong board_get_usable_ram_top(ulong total_size)
-{
-	phys_size_t size;
-	phys_addr_t reg;
-	struct lmb lmb;
-
-	if (!total_size)
-		return gd->ram_top;
-
-	/* found enough not-reserved memory to relocated U-Boot */
-	lmb_init(&lmb);
-	lmb_add(&lmb, gd->ram_base, gd->ram_size);
-	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
-	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
-	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
-
-	if (!reg)
-		reg = gd->ram_top - size;
-
-	return reg + size;
-}
-
 void reset_cpu(void)
 {
 }
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 63aff0474be..c96433be693 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -168,8 +168,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
 
-	if (!CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) &&
-	    env_get("dfu_alt_info"))
+	if (env_get("dfu_alt_info"))
 		return;
 
 	memset(buf, 0, sizeof(buf));
@@ -177,13 +176,14 @@ void set_dfu_alt_info(char *interface, char *devstr)
 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
 	case ZYNQ_BM_SD:
 		snprintf(buf, DFU_ALT_BUF_LEN,
-			 "mmc 0:1=boot.bin fat 0 1;"
-			 "u-boot.img fat 0 1");
+			 "mmc 0=boot.bin fat 0 1;"
+			 "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
 		break;
 	case ZYNQ_BM_QSPI:
 		snprintf(buf, DFU_ALT_BUF_LEN,
 			 "sf 0:0=boot.bin raw 0 0x1500000;"
-			 "u-boot.img raw 0x%x 0x500000",
+			 "%s raw 0x%x 0x500000",
+			 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
 			 CONFIG_SYS_SPI_U_BOOT_OFFS);
 		break;
 	default:
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index 2ab9596248c..e20030ecda7 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -142,9 +142,6 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
 	aes->keysrc = hextoul(argv[6], NULL);
 	aes->dstaddr = hextoul(argv[7], NULL);
 
-	flush_dcache_range((ulong)aes, (ulong)(aes) +
-			   roundup(sizeof(struct aes), ARCH_DMA_MINALIGN));
-
 	if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
 		flush_dcache_range(aes->srcaddr,
 				   (aes->srcaddr +
@@ -169,6 +166,9 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
 						    ARCH_DMA_MINALIGN)));
 	}
 
+	flush_dcache_range((ulong)aes, (ulong)(aes) +
+			   roundup(sizeof(struct aes), ARCH_DMA_MINALIGN));
+
 	ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
 				lower_32_bits((ulong)aes), 0, 0, ret_payload);
 	if (ret || ret_payload[1])
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 57259b60a02..62537760dfa 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -12,8 +12,6 @@
 #include <env.h>
 #include <env_internal.h>
 #include <init.h>
-#include <image.h>
-#include <lmb.h>
 #include <log.h>
 #include <net.h>
 #include <sata.h>
@@ -256,33 +254,6 @@ int dram_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_LMB)
-ulong board_get_usable_ram_top(ulong total_size)
-{
-	phys_size_t size;
-	phys_addr_t reg;
-	struct lmb lmb;
-
-	if (!total_size)
-		return gd->ram_top;
-
-	if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
-		panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
-
-	/* found enough not-reserved memory to relocated U-Boot */
-	lmb_init(&lmb);
-	lmb_add(&lmb, gd->ram_base, gd->ram_size);
-	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
-	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
-	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
-
-	if (!reg)
-		reg = gd->ram_top - size;
-
-	return reg + size;
-}
-#endif
-
 #else
 int dram_init_banksize(void)
 {
@@ -641,8 +612,7 @@ void set_dfu_alt_info(char *interface, char *devstr)
 
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
 
-	if (!CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) &&
-	    env_get("dfu_alt_info"))
+	if (env_get("dfu_alt_info"))
 		return;
 
 	memset(buf, 0, sizeof(buf));
@@ -662,13 +632,13 @@ void set_dfu_alt_info(char *interface, char *devstr)
 		bootseq = mmc_get_env_dev();
 		if (!multiboot)
 			snprintf(buf, DFU_ALT_BUF_LEN,
-				 "mmc %d:1=boot.bin fat %d 1;"
+				 "mmc %d=boot.bin fat %d 1;"
 				 "%s fat %d 1",
 				 bootseq, bootseq,
 				 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
 		else
 			snprintf(buf, DFU_ALT_BUF_LEN,
-				 "mmc %d:1=boot%04d.bin fat %d 1;"
+				 "mmc %d=boot%04d.bin fat %d 1;"
 				 "%s fat %d 1",
 				 bootseq, multiboot, bootseq,
 				 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);