x86: kconfig: Let board select BOARD_EARLY_INIT_F

CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes
and should be not 'default y' for all x86 boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

9 files changed, 5 insertions, 20 deletions

diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig
index f6f3748fc35..945aa43bd28 100644
--- a/board/advantech/som-db5800-som-6867/Kconfig
+++ b/board/advantech/som-db5800-som-6867/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
index 24b8f695ac4..f91ffa13254 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 
 config PCIE_ECAM_BASE
diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig
index fca8b53d026..59f45efcf79 100644
--- a/board/dfi/dfi-bt700/Kconfig
+++ b/board/dfi/dfi-bt700/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 
 config PCIE_ECAM_BASE
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 42615e1e231..64e7c1a08d8 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -16,8 +16,3 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
index 3c3f5d48337..356b92a4546 100644
--- a/board/google/chromebook_samus/samus.c
+++ b/board/google/chromebook_samus/samus.c
@@ -11,8 +11,3 @@ int arch_early_init_r(void)
 {
 	return cpu_run_reference_code();
 }
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index e3baf887833..ed60e442641 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -11,8 +11,3 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
index 95a617b7256..4e7d02161fc 100644
--- a/board/intel/cougarcanyon2/Kconfig
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -21,5 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_FSP
 	select BOARD_ROMSIZE_KB_2048
+	select BOARD_EARLY_INIT_F
 
 endif
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
index b30701afc80..05626a9e921 100644
--- a/board/intel/crownbay/Kconfig
+++ b/board/intel/crownbay/Kconfig
@@ -20,5 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUEENSBAY
 	select BOARD_ROMSIZE_KB_1024
+	select BOARD_EARLY_INIT_F
 
 endif
diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c
index 568bd4db490..2fe1923a9fc 100644
--- a/board/intel/galileo/galileo.c
+++ b/board/intel/galileo/galileo.c
@@ -9,11 +9,6 @@
 #include <asm/arch/device.h>
 #include <asm/arch/quark.h>
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 /*
  * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
  *