diff options
| author | Hai Pham | 2023-02-28 00:02:19 +0100 |
|---|---|---|
| committer | Marek Vasut | 2023-03-18 11:59:45 +0100 |
| commit | 33c3ec22d4d96336d4c0ad9f5e8183a3f3680bfd (patch) | |
| tree | 4d39a98e0af419baaabc6dda1ef4b010151bc027 /board | |
| parent | 72eb1f5e19320ea4919f62341ce077a521d9c278 (diff) | |
ARM: renesas: falcon: Enable RWDT reset for V3U Falcon
Enable RWDT reset on Reset Controller so that it can be used as
reset trigger source for V3U Falcon.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use one current_el() in board_init
Diffstat (limited to 'board')
| -rw-r--r-- | board/renesas/falcon/falcon.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index b7e7fd9003a..ab7464d0ee3 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -83,21 +83,27 @@ int board_early_init_f(void) return 0; } +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 +#define RST_WDTRSTCR (RST_BASE + 0x10) +#define RST_RWDT 0xA55A8002 + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000; - if (current_el() == 3) + if (current_el() == 3) { init_gic_v3(); + /* Enable RWDT reset */ + writel(RST_RWDT, RST_WDTRSTCR); + } + return 0; } -#define RST_BASE 0xE6160000 /* Domain0 */ -#define RST_SRESCR0 (RST_BASE + 0x18) -#define RST_SPRES 0x5AA58000 - void reset_cpu(void) { writel(RST_SPRES, RST_SRESCR0); |