Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

6 files changed, 170 insertions, 76 deletions

diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h
index f7031b347c9..4410f19b76a 100644
--- a/board/avnet/fx12mm/xparameters.h
+++ b/board/avnet/fx12mm/xparameters.h
@@ -46,6 +46,6 @@
 #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
 
 /* FLASH */
-#define XPAR_FLASH_2MX16_MEM0_BASEADDR 0xFFC00000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
 
 #endif
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index d88b3876dc2..ad490c3494c 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2008
  * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,6 +23,9 @@
 
 #include <common.h>
 #include <command.h>
+#if !defined(CONFIG_440)
+#include <asm/4xx_pci.h>
+#endif
 
 #if defined(CONFIG_CMD_BSP)
 
@@ -36,18 +39,24 @@ extern int do_autoscript (cmd_tbl_t *, int, int, char *[]);
  */
 int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	unsigned int *ptr = 0;
+	u32 *ptr = 0;
 	int count = 0;
 	int count2 = 0;
 	char addr[16];
 	char str[] = "\\|/-";
 	char *local_args[2];
+	u32 la, ptm1la;
 
+#if defined(CONFIG_440)
+	ptm1la = in32r(PCIX0_PTM1LA);
+#else
+	ptm1la = in32r(PTM1LA);
+#endif
 	while(1) {
 		/*
 		 * Mark sync address
 		 */
-		ptr = 0;
+		ptr = (u32 *)ptm1la;
 		memset(ptr, 0, 0x20);
 
 		*ptr = 0xffffffff;
@@ -74,7 +83,8 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 
 		printf("\nGot bootcode %08x: ", *ptr);
-		sprintf(addr, "%08x", *ptr & ADDRMASK);
+		la = ptm1la + (*ptr & ADDRMASK);
+		sprintf(addr, "%08x", la);
 
 		switch (*ptr & ~ADDRMASK) {
 		case 0:
@@ -83,8 +93,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			 */
 			printf("booting image at addr 0x%s ...\n", addr);
 			setenv("loadaddr", addr);
-
-			do_bootm (cmdtp, 0, 0, NULL);
+			do_bootm(cmdtp, 0, 0, NULL);
 			break;
 
 		case 1:
@@ -92,7 +101,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			 * Boot image via autoscr
 			 */
 			printf("executing script at addr 0x%s ...\n", addr);
-
 			local_args[0] = addr;
 			local_args[1] = NULL;
 			do_autoscript(cmdtp, 0, 1, local_args);
@@ -103,7 +111,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			 * Call run_cmd
 			 */
 			printf("running command at addr 0x%s ...\n", addr);
-			run_command ((char*)(*ptr & ADDRMASK), 0);
+			run_command((char*)la, 0);
 			break;
 
 		default:
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 38ee74eb4bc..3f0dca087cb 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -26,6 +26,9 @@
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/processor.h>
+#if defined(CONFIG_LOGBUFFER)
+#include <logbuff.h>
+#endif
 
 #include "pmc440.h"
 
@@ -343,14 +346,11 @@ extern env_t *env_ptr;
 
 int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	u32 memsize;
-	u32 pram, env_base;
+	u32 pram, nextbase, base;
 	char *v;
 	u32 param;
 	ulong *lptr;
 
-	memsize = gd->bd->bi_memsize;
-
 	v = getenv("pram");
 	if (v)
 		pram = simple_strtoul(v, NULL, 10);
@@ -359,21 +359,42 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	param = memsize - (pram << 10);
+	base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+	/*
+	 * gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE
+	 */
+	param = base - (pram << 10);
 	printf("PARAM: @%08x\n", param);
+	debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
 
+	/* clear entire PA ram */
 	memset((void*)param, 0, (pram << 10));
-	env_base = memsize - 4096 - ((CONFIG_ENV_SIZE + 4096) & ~(4096-1));
-	memcpy((void*)env_base, env_ptr, CONFIG_ENV_SIZE);
 
-	lptr = (ulong*)memsize;
-	*(--lptr) = CONFIG_ENV_SIZE;
-	*(--lptr) = memsize - env_base;
-	*(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
-	*(--lptr) = 0;
+	/* reserve 4k for pointer field */
+	nextbase = base - 4096;
+	lptr = (ulong*)(base);
+
+	/*
+	 * *(--lptr) = item_size;
+	 * *(--lptr) = base - item_base = distance from field top;
+	 */
+
+	/* env is first (4k aligned) */
+	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+	memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
+	*(--lptr) = base - nextbase;  /* offset | type=0 */
+
+	/* free section */
+	*(--lptr) = nextbase - param; /* size */
+	*(--lptr) = (base - param) | 126; /* offset | type=126 */
 
-	/* make sure data can be accessed through PCI */
-	flush_dcache_range(param, param + (pram << 10) - 1);
+	/* terminate pointer field */
+	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+	*(--lptr) = 0;                /* offset=0 -> terminator */
 	return 0;
 }
 U_BOOT_CMD(
@@ -385,28 +406,11 @@ U_BOOT_CMD(
 
 int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	if (argc > 1) {
-		if (argv[1][0] == '0') {
-			/* assert */
-			printf("self-reset# asserted\n");
-			out_be32((void*)GPIO0_TCR,
-				 in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
-		} else {
-			/* deassert */
-			printf("self-reset# deasserted\n");
-			out_be32((void*)GPIO0_TCR,
-				 in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
-		}
-	} else {
-		printf("self-reset# is %s\n",
-		       in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
-		       "active" : "inactive");
-	}
-
+	in_be32((void*)CONFIG_SYS_RESET_BASE);
 	return 0;
 }
 U_BOOT_CMD(
-	selfreset,	2,	1,	do_selfreset,
+	selfreset,	1,	1,	do_selfreset,
 	"selfreset- assert self-reset# signal\n",
 	NULL
 	);
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index a35f42bd51d..a2eda32ac89 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -220,8 +220,9 @@ int fpga_post_config_fn(int cookie)
 
 	FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
 
-	/* NGCC only: enable ledlink */
-	if ((s = getenv("bd_type")) && !strcmp(s, "ngcc"))
+	/* NGCC/CANDES only: enable ledlink */
+	if ((s = getenv("bd_type")) &&
+	    ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
 		FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
 
 	return rc;
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 013815e2659..8563d7d5f2c 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007-2008
+ * (Cg) Copyright 2007-2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  * Based on board/amcc/sequoia/sequoia.c
  *
@@ -45,9 +45,11 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern void __ft_board_setup(void *blob, bd_t *bd);
 
 ulong flash_get_size(ulong base, int banknum);
 int pci_is_66mhz(void);
+int is_monarch(void);
 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
 			  uchar *buffer, unsigned cnt);
 
@@ -107,9 +109,9 @@ int board_early_init_f(void)
 	 */
 	out32(GPIO0_OR,    0x40000002);
 	out32(GPIO0_TCR,   0x4c90011f);
-	out32(GPIO0_OSRL,  0x28011400);
+	out32(GPIO0_OSRL,  0x28051400);
 	out32(GPIO0_OSRH,  0x55005000);
-	out32(GPIO0_TSRL,  0x08011400);
+	out32(GPIO0_TSRL,  0x08051400);
 	out32(GPIO0_TSRH,  0x55005000);
 	out32(GPIO0_ISR1L, 0x54000000);
 	out32(GPIO0_ISR1H, 0x00000000);
@@ -196,6 +198,23 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#if defined(CONFIG_MISC_INIT_F)
+int misc_init_f(void)
+{
+	struct pci_controller hose;
+	hose.first_busno = 0;
+	hose.last_busno = 0;
+	hose.region_count = 0;
+
+	if (getenv("pciearly") && (!is_monarch())) {
+		printf("PCI:   early target init\n");
+		pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+		pci_target_init(&hose);
+	}
+	return 0;
+}
+#endif
+
 /*
  * misc_init_r.
  */
@@ -207,6 +226,7 @@ int misc_init_r(void)
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
+	unsigned long sdr0_srst0, sdr0_srst1;
 	char *act = getenv("usbact");
 
 	/*
@@ -256,7 +276,7 @@ int misc_init_r(void)
 	/*
 	 * USB suff...
 	 */
-	if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+	if ((act == NULL || strcmp(act, "host") == 0) &&
 	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
 		/* SDR Setting */
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -290,12 +310,46 @@ int misc_init_r(void)
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
-		/* clear resets */
+		/*
+		 * Take USB out of reset:
+		 * -Initial status = all cores are in reset
+		 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+		 * -wait 1 ms
+		 * -deassert reset to PHY
+		 * -wait 1 ms
+		 * -deassert  reset to HOST
+		 * -wait 4 ms
+		 * -deassert all other resets
+		 */
+		mfsdr(SDR0_SRST1, sdr0_srst1);
+		sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |	\
+				SDR0_SRST1_P4OPB0 |	\
+				SDR0_SRST1_OPBA2 |	\
+				SDR0_SRST1_PLB42OPB1 |	\
+				SDR0_SRST1_OPB2PLB40);
+		mtsdr(SDR0_SRST1, sdr0_srst1);
+		udelay(1000);
+
+		mfsdr(SDR0_SRST1, sdr0_srst1);
+		sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+		mtsdr(SDR0_SRST1, sdr0_srst1);
 		udelay(1000);
+
+		mfsdr(SDR0_SRST0, sdr0_srst0);
+		sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+		mtsdr(SDR0_SRST0, sdr0_srst0);
+		udelay(4000);
+
+		/* finally all the other resets */
 		mtsdr(SDR0_SRST1, 0x00000000);
-		udelay(1000);
 		mtsdr(SDR0_SRST0, 0x00000000);
 
+		if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+			/* enable power on USB socket */
+			out_be32((void*)GPIO1_OR,
+				 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+		}
+
 		printf("USB:   Host\n");
 
 	} else if ((strcmp(act, "dev") == 0) ||
@@ -547,14 +601,14 @@ void pci_target_init(struct pci_controller *hose)
 		out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
 		out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 	} else {
-		/* BAR2: default: 16 MB FPGA + registers */
-		out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
+		/* BAR2: default: 4MB FPGA */
+		out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
 		out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 	}
 
 	if (is_monarch()) {
 		/* BAR2: map FPGA registers behind system memory at 1GB */
-		pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
+		pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
 	}
 
 	/*
@@ -562,8 +616,8 @@ void pci_target_init(struct pci_controller *hose)
 	 */
 
 	/* Program the board's vendor id */
-	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
+				   CONFIG_SYS_PCI_SUBSYS_VENDORID);
 
 	/* disabled for PMC405 backward compatibility */
 	/* Configure command register as bus master */
@@ -571,19 +625,19 @@ void pci_target_init(struct pci_controller *hose)
 
 
 	/* 240nS PCI clock */
-	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+	pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
 
 	/* No error reporting */
-	pci_write_config_word(0, PCI_ERREN, 0);
+	pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
 
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 	if (!is_monarch()) {
 		/* Program the board's subsystem id/classcode */
-		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
-				      CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
-		pci_write_config_word(0, PCI_CLASS_SUB_CODE,
-				      CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+					   CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+					   CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
 
 		/* PCI configuration done: release ERREADY */
 		out_be32((void*)GPIO1_OR,
@@ -592,11 +646,14 @@ void pci_target_init(struct pci_controller *hose)
 			 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
 	} else {
 		/* Program the board's subsystem id/classcode */
-		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
-				      CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
-		pci_write_config_word(0, PCI_CLASS_SUB_CODE,
-				      CONFIG_SYS_PCI_CLASSCODE_MONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+					   CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
+		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+					   CONFIG_SYS_PCI_CLASSCODE_MONARCH);
 	}
+
+	/* enable host configuration */
+	pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
@@ -626,6 +683,12 @@ static void wait_for_pci_ready(void)
 {
 	int i;
 	char *s = getenv("pcidelay");
+	/*
+	 * We have our own handling of the pcidelay variable.
+	 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+	 * and adapter devices. For adapter devices we do not
+	 * want this.
+	 */
 	if (s) {
 		int ms = simple_strtoul(s, NULL, 10);
 		printf("PCI:   Waiting for %d ms\n", ms);
@@ -851,7 +914,7 @@ int usb_board_init(void)
 	char *act = getenv("usbact");
 	int i;
 
-	if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+	if ((act == NULL || strcmp(act, "host") == 0) &&
 	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
 		/* enable power on USB socket */
 		out_be32((void*)GPIO1_OR,
@@ -876,3 +939,24 @@ int usb_board_init_fail(void)
 	return 0;
 }
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
+
+	__ft_board_setup(blob, bd);
+
+	/*
+	 * Disable PCI in non-monarch mode.
+	 */
+	if (!is_monarch()) {
+		rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
index d834f258571..295cec1e330 100644
--- a/board/esd/pmc440/pmc440.h
+++ b/board/esd/pmc440/pmc440.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  *
  * See file CREDITS for list of people who contributed to this
@@ -24,8 +24,7 @@
 #ifndef __PMC440_H__
 #define __PMC440_H__
 
-
-/*-----------------------------------------------------------------------
+/*
  * GPIOs
  */
 #define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
@@ -41,9 +40,10 @@
 #define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
 #define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
 #define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
-#define GPIO0_SELF_RST            (0x80000000 >> 6)       /* GPIO6  OD */
 
-/* FPGA programming pin configuration */
+/*
+ * FPGA programming pin configuration
+ */
 #define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
 #define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
 #define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
@@ -51,7 +51,7 @@
 #define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
 #define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
 
-/*-----------------------------------------------------------------------
+/*
  * FPGA interface
  */
 #define FPGA_BA CONFIG_SYS_FPGA_BASE0
@@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
 #define RESET_OUT   (1 << 19)
 #define IRIGB_R_OUT (1 << 14)
 
-
 /* status register */
 #define STATUS_VERSION_SHIFT 24
 #define STATUS_VERSION_MASK  0xff000000
@@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
 #define STATUS_FIFO_ISF      (1 <<  9)
 #define STATUS_HOST_ISF      (1 <<  8)
 
-
 /* inputs */
 #define RESET_IN    (1 << 0)
 #define CLOCK_IN    (1 << 1)
 #define IRIGB_R_IN  (1 << 5)
 
-
 /* hostctrl register */
 #define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
 #define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
@@ -137,7 +134,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
 #define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
 #define NGCC_CTRL_FPGARST_N    (1 <<  2)
 
-/*-----------------------------------------------------------------------
+/*
  * FPGA to PPC interrupt
  */
 #define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */