Merge branch 'master' of git://www.denx.de/git/u-boot-imx

12 files changed, 652 insertions, 127 deletions

diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index f1e5eb433a3..c7c21f392bb 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -112,7 +112,7 @@ static void setup_iomux_spi(void)
 #ifdef CONFIG_USB_EHCI_MX5
 #define MX51EVK_USBH1_HUB_RST	IMX_GPIO_NR(1, 7)
 #define MX51EVK_USBH1_STP	IMX_GPIO_NR(1, 27)
-#define MX51EVK_USB_CLK_EN_B	IMX_GPIO_NR(2, 2)
+#define MX51EVK_USB_CLK_EN_B	IMX_GPIO_NR(2, 1)
 #define MX51EVK_USB_PHY_RESET	IMX_GPIO_NR(2, 5)
 
 static void setup_usb_h1(void)
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 3a5b26dde74..98ccdb785b3 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -16,6 +16,7 @@
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -213,6 +214,43 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+
+	/*
+	 * set daisy chain for otg_pin_id on 6q.
+	 * for 6dl, this bit is reserved
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 1);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 0)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -226,6 +264,10 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index ac3757f0744..2f7198d3bfd 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -29,6 +29,7 @@
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 #include <asm/arch/mx6-ddr.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -537,6 +538,69 @@ int board_eth_init(bd_t *bis)
 	return cpu_eth_init(bis);
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
+	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+
+	/*
+	 * set daisy chain for otg_pin_id on 6q.
+	 * for 6dl, this bit is reserved
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+
+	imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+					 ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		if (on)
+			gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+		else
+			gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -557,6 +621,10 @@ int board_init(void)
 #endif
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 3834eec60e8..838ea6c0f0d 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -308,11 +308,6 @@ int board_init(void)
 	return 0;
 }
 
-u32 get_board_rev(void)
-{
-	return get_cpu_rev();
-}
-
 int checkboard(void)
 {
 	puts("Board: MX6SLEVK\n");
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index d6a584745bd..97128127fbe 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -401,7 +401,7 @@ static void ccgr_init(void)
 	writel(0x0030FC03, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
 	writel(0x3FF00000, &ccm->CCGR3);
-	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003FF, &ccm->CCGR6);
 }
diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile
index 6fba17718b7..6893b6311d6 100644
--- a/board/kosagi/novena/Makefile
+++ b/board/kosagi/novena/Makefile
@@ -8,4 +8,5 @@ ifdef CONFIG_SPL_BUILD
 obj-y	:= novena_spl.o
 else
 obj-y	:= novena.o
+obj-$(CONFIG_VIDEO_IPUV3)	+= video.o
 endif
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index 6add9e52653..69f5be3b9c1 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -36,11 +36,9 @@
 #include <power/pfuze100_pmic.h>
 #include <stdio_dev.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+#include "novena.h"
 
-#define NOVENA_BUTTON_GPIO	IMX_GPIO_NR(4, 14)
-#define NOVENA_SD_WP		IMX_GPIO_NR(1, 2)
-#define NOVENA_SD_CD		IMX_GPIO_NR(1, 4)
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * GPIO button
@@ -154,87 +152,10 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-/*
- * Video over HDMI
- */
-#if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(struct display_info_t const *dev)
-{
-	imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {
-	{
-		/* HDMI Output */
-		.bus	= -1,
-		.addr	= 0,
-		.pixfmt	= IPU_PIX_FMT_RGB24,
-		.detect	= detect_hdmi,
-		.enable	= enable_hdmi,
-		.mode	= {
-			.name           = "HDMI",
-			.refresh        = 60,
-			.xres           = 1024,
-			.yres           = 768,
-			.pixclock       = 15385,
-			.left_margin    = 220,
-			.right_margin   = 40,
-			.upper_margin   = 21,
-			.lower_margin   = 7,
-			.hsync_len      = 60,
-			.vsync_len      = 10,
-			.sync           = FB_SYNC_EXT,
-			.vmode          = FB_VMODE_NONINTERLACED
-		}
-	}
-};
-
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	enable_ipu_clock();
-	imx_setup_hdmi();
-
-	/* Turn on LDB0,IPU,IPU DI0 clocks */
-	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-
-	/* set LDB0, LDB1 clk select to 011/011 */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-			MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
-			(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-			(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
-
-	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-
-	setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
-		     MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-
-	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
-	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
-	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-	       IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-	       IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
-	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
-	       &iomux->gpr[2]);
-
-	clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
-			IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-}
-#endif
-
 int board_early_init_f(void)
 {
 #if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
+	setup_display_clock();
 #endif
 
 	return 0;
@@ -252,6 +173,14 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display_lvds();
+#endif
+	return 0;
+}
+
 int checkboard(void)
 {
 	puts("Board: Novena 4x\n");
diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h
new file mode 100644
index 00000000000..8f11583c2d9
--- /dev/null
+++ b/board/kosagi/novena/novena.h
@@ -0,0 +1,33 @@
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__
+#define __BOARD_KOSAGI_NOVENA_NOVENA_H__
+
+#define NOVENA_AUDIO_PWRON		IMX_GPIO_NR(5, 17)
+#define NOVENA_BACKLIGHT_PWM_GPIO	IMX_GPIO_NR(4, 29)
+#define NOVENA_BACKLIGHT_PWR_GPIO	IMX_GPIO_NR(4, 15)
+#define NOVENA_BUTTON_GPIO		IMX_GPIO_NR(4, 14)
+#define NOVENA_FPGA_RESET_N_GPIO	IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD		IMX_GPIO_NR(5, 4)
+#define NOVENA_ITE6251_PWR_GPIO		IMX_GPIO_NR(5, 28)
+#define NOVENA_PCIE_DISABLE_GPIO	IMX_GPIO_NR(2, 16)
+#define NOVENA_PCIE_POWER_ON_GPIO	IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_RESET_GPIO		IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_WAKE_UP_GPIO	IMX_GPIO_NR(3, 22)
+#define NOVENA_SD_CD			IMX_GPIO_NR(1, 4)
+#define NOVENA_SD_WP			IMX_GPIO_NR(1, 2)
+
+#define NOVENA_IT6251_I2C_BUS	2
+#define NOVENA_IT6251_CHIPADDR	0x5c
+#define NOVENA_IT6251_LVDSADDR	0x5e
+
+void setup_display_clock(void);
+void setup_display_lvds(void);
+
+#endif	/* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index c07735ad03a..b1688e02958 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -25,6 +25,8 @@
 
 #include <asm/arch/mx6-ddr.h>
 
+#include "novena.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL						\
@@ -68,14 +70,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
-#define NOVENA_AUDIO_PWRON		IMX_GPIO_NR(5, 17)
-#define NOVENA_FPGA_RESET_N_GPIO	IMX_GPIO_NR(5, 7)
-#define NOVENA_HDMI_GHOST_HPD		IMX_GPIO_NR(5, 4)
-#define NOVENA_PCIE_RESET_GPIO		IMX_GPIO_NR(3, 29)
-#define NOVENA_PCIE_POWER_ON_GPIO	IMX_GPIO_NR(7, 12)
-#define NOVENA_PCIE_WAKE_UP_GPIO	IMX_GPIO_NR(3, 22)
-#define NOVENA_PCIE_DISABLE_GPIO	IMX_GPIO_NR(2, 16)
-
 /*
  * Audio
  */
@@ -392,6 +386,13 @@ static void novena_spl_setup_iomux_uart(void)
 static iomux_v3_cfg_t hdmi_pads[] = {
 	/* "Ghost HPD" pin */
 	MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* LCD_PWR_CTL */
+	MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* LCD_BL_ON */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPIO_PWM1 */
+	MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void novena_spl_setup_iomux_video(void)
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
new file mode 100644
index 00000000000..3bb1b7180b5
--- /dev/null
+++ b/board/kosagi/novena/video.c
@@ -0,0 +1,456 @@
+/*
+ * Novena video output support
+ *
+ * IT6251 code based on code Copyright (C) 2014 Sean Cross
+ * from https://github.com/xobs/novena-linux.git commit
+ * 3d85836ee1377d445531928361809612aa0a18db
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+#define IT6251_VENDOR_ID_LOW				0x00
+#define IT6251_VENDOR_ID_HIGH				0x01
+#define IT6251_DEVICE_ID_LOW				0x02
+#define IT6251_DEVICE_ID_HIGH				0x03
+#define IT6251_SYSTEM_STATUS				0x0d
+#define IT6251_SYSTEM_STATUS_RINTSTATUS			(1 << 0)
+#define IT6251_SYSTEM_STATUS_RHPDSTATUS			(1 << 1)
+#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE		(1 << 2)
+#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK		(1 << 3)
+#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK		(1 << 4)
+#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK		(1 << 5)
+#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK		(1 << 6)
+#define IT6251_REF_STATE				0x0e
+#define IT6251_REF_STATE_MAIN_LINK_DISABLED		(1 << 0)
+#define IT6251_REF_STATE_AUX_CHANNEL_READ		(1 << 1)
+#define IT6251_REF_STATE_CR_PATTERN			(1 << 2)
+#define IT6251_REF_STATE_EQ_PATTERN			(1 << 3)
+#define IT6251_REF_STATE_NORMAL_OPERATION		(1 << 4)
+#define IT6251_REF_STATE_MUTED				(1 << 5)
+
+#define IT6251_REG_PCLK_CNT_LOW				0x57
+#define IT6251_REG_PCLK_CNT_HIGH			0x58
+
+#define IT6521_RETRY_MAX				20
+
+static int it6251_is_stable(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+	int status;
+	int clkcnt;
+	int rpclkcnt;
+	int refstate;
+
+	rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
+		   ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+	debug("RPCLKCnt: %d\n", rpclkcnt);
+
+	status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+	debug("System status: 0x%02x\n", status);
+
+	clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+		 ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+		  0x0f00);
+	debug("Clock: 0x%02x\n", clkcnt);
+
+	refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+	debug("Ref Link State: 0x%02x\n", refstate);
+
+	if ((refstate & 0x1f) != 0)
+		return 0;
+
+	/* If video is muted, that's a failure */
+	if (refstate & IT6251_REF_STATE_MUTED)
+		return 0;
+
+	if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
+		return 0;
+
+	return 1;
+}
+
+static int it6251_ready(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+
+	/* Test if the IT6251 came out of reset by reading ID regs. */
+	if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+		return 0;
+	if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+		return 0;
+
+	return 1;
+}
+
+static void it6251_program_regs(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+
+	i2c_reg_write(caddr, 0x05, 0x00);
+	mdelay(1);
+
+	/* set LVDSRX address, and enable */
+	i2c_reg_write(caddr, 0xfd, 0xbc);
+	i2c_reg_write(caddr, 0xfe, 0x01);
+
+	/*
+	 * LVDSRX
+	 */
+	/* This write always fails, because the chip goes into reset */
+	/* reset LVDSRX */
+	i2c_reg_write(laddr, 0x05, 0xff);
+	i2c_reg_write(laddr, 0x05, 0x00);
+
+	/* reset LVDSRX PLL */
+	i2c_reg_write(laddr, 0x3b, 0x42);
+	i2c_reg_write(laddr, 0x3b, 0x43);
+
+	/* something with SSC PLL */
+	i2c_reg_write(laddr, 0x3c, 0x08);
+	/* don't swap links, but writing reserved registers */
+	i2c_reg_write(laddr, 0x0b, 0x88);
+
+	/* JEIDA, 8-bit depth  0x11, orig 0x42 */
+	i2c_reg_write(laddr, 0x2c, 0x01);
+	/* "reserved" */
+	i2c_reg_write(laddr, 0x32, 0x04);
+	/* "reserved" */
+	i2c_reg_write(laddr, 0x35, 0xe0);
+	/* "reserved" + clock delay */
+	i2c_reg_write(laddr, 0x2b, 0x24);
+
+	/* reset LVDSRX pix clock */
+	i2c_reg_write(laddr, 0x05, 0x02);
+	i2c_reg_write(laddr, 0x05, 0x00);
+
+	/*
+	 * DPTX
+	 */
+	/* set for two lane mode, normal op, no swapping, no downspread */
+	i2c_reg_write(caddr, 0x16, 0x02);
+
+	/* some AUX channel EDID magic */
+	i2c_reg_write(caddr, 0x23, 0x40);
+
+	/* power down lanes 3-0 */
+	i2c_reg_write(caddr, 0x5c, 0xf3);
+
+	/* enable DP scrambling, change EQ CR phase */
+	i2c_reg_write(caddr, 0x5f, 0x06);
+
+	/* color mode RGB, pclk/2 */
+	i2c_reg_write(caddr, 0x60, 0x02);
+	/* dual pixel input mode, no EO swap, no RGB swap */
+	i2c_reg_write(caddr, 0x61, 0x04);
+	/* M444B24 video format */
+	i2c_reg_write(caddr, 0x62, 0x01);
+
+	/* vesa range / not interlace / vsync high / hsync high */
+	i2c_reg_write(caddr, 0xa0, 0x0F);
+
+	/* hpd event timer set to 1.6-ish ms */
+	i2c_reg_write(caddr, 0xc9, 0xf5);
+
+	/* more reserved magic */
+	i2c_reg_write(caddr, 0xca, 0x4d);
+	i2c_reg_write(caddr, 0xcb, 0x37);
+
+	/* enhanced framing mode, auto video fifo reset, video mute disable */
+	i2c_reg_write(caddr, 0xd3, 0x03);
+
+	/* "vidstmp" and some reserved stuff */
+	i2c_reg_write(caddr, 0xd4, 0x45);
+
+	/* queue number -- reserved */
+	i2c_reg_write(caddr, 0xe7, 0xa0);
+	/* info frame packets  and reserved */
+	i2c_reg_write(caddr, 0xe8, 0x33);
+	/* more AVI stuff */
+	i2c_reg_write(caddr, 0xec, 0x00);
+
+	/* select PC master reg for aux channel? */
+	i2c_reg_write(caddr, 0x23, 0x42);
+
+	/* send PC request commands */
+	i2c_reg_write(caddr, 0x24, 0x00);
+	i2c_reg_write(caddr, 0x25, 0x00);
+	i2c_reg_write(caddr, 0x26, 0x00);
+
+	/* native aux read */
+	i2c_reg_write(caddr, 0x2b, 0x00);
+	/* back to internal */
+	i2c_reg_write(caddr, 0x23, 0x40);
+
+	/* voltage swing level 3 */
+	i2c_reg_write(caddr, 0x19, 0xff);
+	/* pre-emphasis level 3 */
+	i2c_reg_write(caddr, 0x1a, 0xff);
+
+	/* start link training */
+	i2c_reg_write(caddr, 0x17, 0x01);
+}
+
+static int it6251_init(void)
+{
+	const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+	int reg;
+	int tries, retries = 0;
+
+	for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
+		/* Program the chip. */
+		it6251_program_regs();
+
+		/* Wait for video stable. */
+		for (tries = 0; tries < 100; tries++) {
+			reg = i2c_reg_read(caddr, 0x17);
+			/* Test Link CFG, STS, LCS read done. */
+			if ((reg & 0xe0) != 0xe0) {
+				/* Not yet, wait a bit more. */
+				mdelay(2);
+				continue;
+			}
+
+			/* Test if the video input is stable. */
+			if (it6251_is_stable())
+				return 0;
+		}
+		/*
+		 * If we couldn't stabilize, requeue and try again,
+		 * because it means that the LVDS channel isn't
+		 * stable yet.
+		 */
+		printf("Display didn't stabilize.\n");
+		printf("This may be because the LVDS port is still in powersave mode.\n");
+		mdelay(50);
+	}
+
+	return -EINVAL;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int lvds_enabled;
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	if (lvds_enabled)
+		return;
+
+	/* ITE IT6251 power enable. */
+	gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
+	mdelay(10);
+	gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
+	mdelay(20);
+	lvds_enabled = 1;
+}
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+	int ret, loops = 250;
+
+	enable_lvds(dev);
+
+	ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+	if (ret) {
+		puts("Cannot select IT6251 I2C bus.\n");
+		return 0;
+	}
+
+	/* Wait up-to ~250 mS for the LVDS to come up. */
+	while (--loops) {
+		ret = it6251_ready();
+		if (ret)
+			return ret;
+
+		mdelay(1);
+	}
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {
+	{
+		/* HDMI Output */
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_hdmi,
+		.enable	= enable_hdmi,
+		.mode	= {
+			.name		= "HDMI",
+			.refresh	= 60,
+			.xres		= 1024,
+			.yres		= 768,
+			.pixclock	= 15384,
+			.left_margin	= 220,
+			.right_margin	= 40,
+			.upper_margin	= 21,
+			.lower_margin	= 7,
+			.hsync_len	= 60,
+			.vsync_len	= 10,
+			.sync		= FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED
+		},
+	}, {
+		/* LVDS Output: N133HSE-EA1 Rev. C1 */
+		.bus	= -1,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_lvds,
+		.enable	= enable_lvds,
+		.mode	= {
+			.name		= "Chimei-FHD",
+			.refresh	= 60,
+			.xres		= 1920,
+			.yres		= 1080,
+			.pixclock	= 15384,
+			.left_margin	= 148,
+			.right_margin	= 88,
+			.upper_margin	= 36,
+			.lower_margin	= 4,
+			.hsync_len	= 44,
+			.vsync_len	= 5,
+			.sync		= FB_SYNC_HOR_HIGH_ACT |
+					  FB_SYNC_VERT_HIGH_ACT |
+					  FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED,
+		},
+	},
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_vpll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+void setup_display_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_ipu_clock();
+	enable_vpll();
+	imx_setup_hdmi();
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	/* Switch LDB DI0 to PLL5 (Video PLL) */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+			(0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+	/* LDB clock div by 3.5 */
+	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	/* DI0 clock derived from ldb_di0_clk */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+			);
+
+	/* Enable both LVDS channels, both connected to DI0. */
+	writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+	       IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+			IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
+			(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+			(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+			);
+}
+
+void setup_display_lvds(void)
+{
+	int ret;
+
+	ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+	if (ret) {
+		puts("Cannot select LVDS-to-eDP I2C bus.\n");
+		return;
+	}
+
+	/* The IT6251 should be ready now, if it's not, it's not connected. */
+	ret = it6251_ready();
+	if (!ret)
+		return;
+
+	/* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
+	ret = it6251_init();
+	if (!ret) {
+		/* Backlight power enable. */
+		gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
+		/* PWM backlight pin, always on for full brightness. */
+		gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
+	}
+}
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
index 313ab20e26e..65cbbf15b73 100644
--- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -78,33 +78,3 @@ int board_init(void)
 
 	return 0;
 }
-
-/* Fine-tune the DRAM configuration. */
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-{
-	/* Enable Auto Precharge. */
-	dram_vals[3] |= 1 << 8;
-	/* Enable Fast Writes. */
-	dram_vals[5] |= 1 << 8;
-	/* tEMRS = 3*tCK */
-	dram_vals[10] &= ~(0x3 << 8);
-	dram_vals[10] |= (0x3 << 8);
-	/* CASLAT = 3*tCK */
-	dram_vals[11] &= ~(0x3 << 0);
-	dram_vals[11] |= (0x3 << 0);
-	/* tCKE = 1*tCK */
-	dram_vals[12] &= ~(0x7 << 0);
-	dram_vals[12] |= (0x1 << 0);
-	/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
-	dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
-	dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
-	/* tDAL = 6*tCK */
-	dram_vals[15] &= ~(0xf << 16);
-	dram_vals[15] |= (0x6 << 16);
-	/* tREF = 1040*tCK */
-	dram_vals[26] &= ~0xffff;
-	dram_vals[26] |= 0x0410;
-	/* tRAS_MAX = 9334*tCK */
-	dram_vals[32] &= ~0xffff;
-	dram_vals[32] |= 0x2475;
-}
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c
index 5272dfa4e67..de3b0e4c8b0 100644
--- a/board/olimex/mx23_olinuxino/spl_boot.c
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -89,3 +89,33 @@ void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
 	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	/* Enable Auto Precharge. */
+	dram_vals[3] |= 1 << 8;
+	/* Enable Fast Writes. */
+	dram_vals[5] |= 1 << 8;
+	/* tEMRS = 3*tCK */
+	dram_vals[10] &= ~(0x3 << 8);
+	dram_vals[10] |= (0x3 << 8);
+	/* CASLAT = 3*tCK */
+	dram_vals[11] &= ~(0x3 << 0);
+	dram_vals[11] |= (0x3 << 0);
+	/* tCKE = 1*tCK */
+	dram_vals[12] &= ~(0x7 << 0);
+	dram_vals[12] |= (0x1 << 0);
+	/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+	dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+	dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+	/* tDAL = 6*tCK */
+	dram_vals[15] &= ~(0xf << 16);
+	dram_vals[15] |= (0x6 << 16);
+	/* tREF = 1040*tCK */
+	dram_vals[26] &= ~0xffff;
+	dram_vals[26] |= 0x0410;
+	/* tRAS_MAX = 9334*tCK */
+	dram_vals[32] &= ~0xffff;
+	dram_vals[32] |= 0x2475;
+}