Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>

8 files changed, 72 insertions, 38 deletions

diff --git a/board/bitmain/antminer_s9/Makefile b/board/bitmain/antminer_s9/Makefile
index 93a1e77f72b..1af01d6d808 100644
--- a/board/bitmain/antminer_s9/Makefile
+++ b/board/bitmain/antminer_s9/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-y	:= board.o
+obj-y	+= ../../xilinx/common/board.o
 
 # Remove quotes
 hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
index becadd2ca74..cc100b0f422 100644
--- a/board/topic/zynq/Makefile
+++ b/board/topic/zynq/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y	:= board.o
+obj-y	+= ../../xilinx/common/board.o
 
 # Remove quotes
 hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index e83c692f217..294a59df77d 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -8,6 +8,8 @@
 #include <asm/sections.h>
 #include <dm/uclass.h>
 #include <i2c.h>
+#include <linux/sizes.h>
+#include "board.h"
 
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
@@ -71,3 +73,16 @@ void *board_fdt_blob_setup(void)
 	return NULL;
 }
 #endif
+
+int board_late_init_xilinx(void)
+{
+	ulong initrd_hi;
+
+	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
+	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	initrd_hi = round_down(initrd_hi, SZ_16M);
+	env_set_addr("initrd_high", (void *)initrd_hi);
+
+	return 0;
+}
diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h
new file mode 100644
index 00000000000..180dfbca108
--- /dev/null
+++ b/board/xilinx/common/board.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#ifndef _BOARD_XILINX_COMMON_BOARD_H
+#define _BOARD_XILINX_COMMON_BOARD_H
+
+int board_late_init_xilinx(void);
+
+#endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 75aedb09292..483e3ce2f79 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -16,7 +16,7 @@
 #include <dm/device.h>
 #include <dm/uclass.h>
 #include <versalpl.h>
-#include <linux/sizes.h>
+#include "../common/board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -82,9 +82,23 @@ int board_early_init_r(void)
 	return 0;
 }
 
-int board_late_init(void)
+static u8 versal_get_bootmode(void)
 {
+	u8 bootmode;
 	u32 reg = 0;
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+int board_late_init(void)
+{
 	u8 bootmode;
 	struct udevice *dev;
 	int bootseq = -1;
@@ -93,19 +107,13 @@ int board_late_init(void)
 	const char *mode;
 	char *new_targets;
 	char *env_targets;
-	ulong initrd_hi;
 
 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 		debug("Saved variables - Skipping\n");
 		return 0;
 	}
 
-	reg = readl(&crp_base->boot_mode_usr);
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
+	bootmode = versal_get_bootmode();
 
 	puts("Bootmode: ");
 	switch (bootmode) {
@@ -200,13 +208,7 @@ int board_late_init(void)
 
 	env_set("boot_targets", new_targets);
 
-	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
-	initrd_hi = round_down(initrd_hi, SZ_16M);
-	env_set_addr("initrd_high", (void *)initrd_hi);
-
-	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
-	return 0;
+	return board_late_init_xilinx();
 }
 
 int dram_init_banksize(void)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 420a5ca6631..2164eac8d51 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -17,6 +17,7 @@
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include "../common/board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -76,9 +77,7 @@ int board_late_init(void)
 
 	env_set("boot_targets", new_targets);
 
-	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
-	return 0;
+	return board_late_init_xilinx();
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
index 4805e5a3b91..383e3d0c7e1 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -363,6 +363,7 @@ static unsigned long psu_mio_init_data(void)
 	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
 	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
 	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
@@ -408,7 +409,7 @@ static unsigned long psu_mio_init_data(void)
 	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
 	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
 	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
-	psu_mask_write(0xFF180204, 0x7B3F003FU, 0x52240000U);
+	psu_mask_write(0xFF180204, 0x7B3F007FU, 0x52240000U);
 	psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U);
 	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
 	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 3c92b1a5825..a2a0d563318 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -26,7 +26,7 @@
 #include <zynqmppl.h>
 #include <zynqmp_firmware.h>
 #include <g_dnl.h>
-#include <linux/sizes.h>
+#include "../common/board.h"
 
 #include "pm_cfg_obj.h"
 
@@ -552,9 +552,26 @@ static int set_fdtfile(void)
 	return 0;
 }
 
-int board_late_init(void)
+static u8 zynqmp_get_bootmode(void)
 {
+	u8 bootmode;
 	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+int board_late_init(void)
+{
 	u8 bootmode;
 	struct udevice *dev;
 	int bootseq = -1;
@@ -564,7 +581,6 @@ int board_late_init(void)
 	char *new_targets;
 	char *env_targets;
 	int ret;
-	ulong initrd_hi;
 
 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 	usb_ether_init();
@@ -579,14 +595,7 @@ int board_late_init(void)
 	if (ret)
 		return ret;
 
-	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
-	if (ret)
-		return -EINVAL;
-
-	if (reg >> BOOT_MODE_ALT_SHIFT)
-		reg >>= BOOT_MODE_ALT_SHIFT;
-
-	bootmode = reg & BOOT_MODES_MASK;
+	bootmode = zynqmp_get_bootmode();
 
 	puts("Bootmode: ");
 	switch (bootmode) {
@@ -691,15 +700,9 @@ int board_late_init(void)
 
 	env_set("boot_targets", new_targets);
 
-	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
-	initrd_hi = round_down(initrd_hi, SZ_16M);
-	env_set_addr("initrd_high", (void *)initrd_hi);
-
-	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
-
 	reset_reason();
 
-	return 0;
+	return board_late_init_xilinx();
 }
 #endif