diff options
| author | Hugo Dubois | 2023-12-01 15:56:12 +0100 |
|---|---|---|
| committer | Christophe Leroy | 2024-04-18 15:47:46 +0200 |
| commit | 8ec8fd6983b499faa29b7469ac666aad93b57ec0 (patch) | |
| tree | 2193d2e46c326afd514bd4c378e01ead7680d1bb /board | |
| parent | b47fb22108946426d3e889dab9c5476f3ec2e357 (diff) | |
board: cssi: Initialise port F on MIAE
When equipped with the SRSA audio board, MIAE equipment
has an additional port called port F.
Initialise that port just like other ports of the board, so
that it is already configured when starting Linux kernel.
Signed-off-by: Hugo Dubois <hugo.dubois.ext@csgroup.eu>
Reviewed-by: CASAUBON Jean Michel <jean-michel.casaubon@csgroup.eu>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'board')
| -rw-r--r-- | board/cssi/common/common.c | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c index 7ecf7726209..6848efd43be 100644 --- a/board/cssi/common/common.c +++ b/board/cssi/common/common.c @@ -208,12 +208,44 @@ void misc_init_r_common(void) } } +static void iop_setup_fpgam_common(void) +{ + u8 far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; + + if (far_id == FAR_CASRSA) { + /* + * PFDIR[15] = 0 [0x01] + * PFDIR[14] = 1 [0x02] + * PFDIR[13] = 1 [0x04] + */ + clrsetbits_8(ADDR_FPGA_R_BASE + 0x37, 0x01, 0x06); + /* + * PFODR[15] = 1 [0x01] + * PFODR[14] = 0 [0x02] + * PFODR[13] = 0 [0x04] + */ + clrsetbits_8(ADDR_FPGA_R_BASE + 0x39, 0x06, 0x01); + /* + * PFDAT[15] = 0 [0x01] + * PFDAT[14] = 1 [0x02] + * PFDAT[13] = 1 [0x04] + * PFDAT[12] = 1 [0x08] + */ + clrsetbits_8(ADDR_FPGA_R_BASE + 0x3B, 0x01, 0x0E); + + /* Setup TOR_OUT */ + out_8(ADDR_FPGA_R_BASE + 0x32, 0x2A); + } +} + void iop_setup_common(void) { u8 type = in_8(ADDR_FPGA_R_BASE); - if (type == TYPE_MCR) + if (type == TYPE_MCR) { iop_setup_mcr(); - else if (type == TYPE_MIAE) + } else if (type == TYPE_MIAE) { iop_setup_miae(); + iop_setup_fpgam_common(); + } } |