diff options
| author | Marek Vasut | 2017-05-02 20:27:41 +0200 |
|---|---|---|
| committer | Tom Rini | 2017-06-29 13:30:28 -0400 |
| commit | ae625ae5a14f63400b8e5ee901a27248037a2339 (patch) | |
| tree | 943eb63d7f3989a5eaa893019e516bf5209d5404 /board | |
| parent | f1d56dffd7f1a112482cdbe4e0ac2076e1eb3fe1 (diff) | |
ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding
According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/aries/ma5d4evk/ma5d4evk.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c index 81463712fa8..dd74e29b8ea 100644 --- a/board/aries/ma5d4evk/ma5d4evk.c +++ b/board/aries/ma5d4evk/ma5d4evk.c @@ -349,7 +349,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | ATMEL_MPDDRC_CR_NB_8BANKS | ATMEL_MPDDRC_CR_NDQS_DISABLED | - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | ATMEL_MPDDRC_CR_UNAL_SUPPORTED); ddr2->rtr = 0x2b0; |