diff options
author | Tom Rini | 2021-06-11 08:29:34 -0400 |
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committer | Tom Rini | 2021-06-11 08:29:34 -0400 |
commit | c4737cd594b5c4c47aff789fc53f7dd36ed03c94 (patch) | |
tree | 595a6e51448b831b871f0215d4cd80369a31ab33 /board | |
parent | cf066a20c3ec063d019a991cc32ba8ad95a39780 (diff) | |
parent | 6bb577dbb30f3fcf47679328a1b77edc3d0c0b79 (diff) |
Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.07-rc5
zynqmp:
- Fix ANALOG_BUS value after powerup
- Disable EFI_CAPSULE_ON_DISK_EARLY
zynqmp-gqspi:
- Fix write issue
Diffstat (limited to 'board')
-rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d05f0b2e120..ee4d0c85e6b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -287,6 +287,17 @@ int board_early_init_f(void) if (ret) return ret; + /* + * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon + * supply sense channel to SysMon supply registers inside the IP. + * This register must be programmed to complete SysMon IP + * configuration. The default register configuration after + * power-up is incorrect. Hence, fix this by writing the + * correct value - 0x3210. + */ + writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL, + ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS); + /* Delay is required for clocks to be propagated */ udelay(1000000); #endif |