diff options
author | Allen Martin | 2013-01-16 13:11:21 +0000 |
---|---|---|
committer | Tom Warren | 2013-01-17 09:07:23 -0700 |
commit | d3f8752ed60cbd18022aee0afb7784754c125170 (patch) | |
tree | 699247a7c5f46db4e96ed65748875abf41d1abe1 /board | |
parent | d08b9e9c7e22c205075d16eec42f452b1daae277 (diff) |
tegra: fdt: remove clocks nodes
These nodes are unused.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/avionic-design/dts/tegra20-medcom-wide.dts | 14 | ||||
-rw-r--r-- | board/avionic-design/dts/tegra20-plutux.dts | 14 | ||||
-rw-r--r-- | board/avionic-design/dts/tegra20-tec.dts | 14 | ||||
-rw-r--r-- | board/compal/dts/tegra20-paz00.dts | 13 | ||||
-rw-r--r-- | board/compulab/dts/tegra20-trimslice.dts | 13 | ||||
-rw-r--r-- | board/nvidia/dts/tegra20-harmony.dts | 13 | ||||
-rw-r--r-- | board/nvidia/dts/tegra20-seaboard.dts | 10 | ||||
-rw-r--r-- | board/nvidia/dts/tegra20-ventana.dts | 13 | ||||
-rw-r--r-- | board/nvidia/dts/tegra20-whistler.dts | 10 | ||||
-rw-r--r-- | board/nvidia/dts/tegra30-cardhu.dts | 13 |
10 files changed, 0 insertions, 127 deletions
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index 70587a6558e..e46afbeab38 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -14,16 +14,6 @@ reg = <0x00000000 0x20000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - - osc { - clock-frequency = <12000000>; - }; - }; - host1x { status = "okay"; @@ -37,10 +27,6 @@ }; }; - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006300 { clock-frequency = <216000000>; }; diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index 78c394f9358..3e6cce013e4 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -14,20 +14,6 @@ reg = <0x00000000 0x20000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006300 { clock-frequency = <216000000>; }; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index cdb752776c4..8135eebd65a 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -14,16 +14,6 @@ reg = <0x00000000 0x20000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - - osc { - clock-frequency = <12000000>; - }; - }; - host1x { status = "okay"; @@ -37,10 +27,6 @@ }; }; - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006300 { clock-frequency = <216000000>; }; diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts index afebbe59c65..0fef7136fcd 100644 --- a/board/compal/dts/tegra20-paz00.dts +++ b/board/compal/dts/tegra20-paz00.dts @@ -14,19 +14,6 @@ reg = <0x00000000 0x20000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006000 { clock-frequency = < 216000000 >; }; diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts index 4450674a759..c8a4dd4e411 100644 --- a/board/compulab/dts/tegra20-trimslice.dts +++ b/board/compulab/dts/tegra20-trimslice.dts @@ -15,19 +15,6 @@ reg = <0x00000000 0x40000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006000 { clock-frequency = <216000000>; }; diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index 5645a8d4772..b456406182b 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -15,19 +15,6 @@ reg = <0x00000000 0x40000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006300 { clock-frequency = < 216000000 >; }; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index dd98ca48e9f..5fd8ae29982 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -45,16 +45,6 @@ }; }; - clocks { - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006300 { clock-frequency = < 216000000 >; }; diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts index 38b7b1355d3..3e5e39da632 100644 --- a/board/nvidia/dts/tegra20-ventana.dts +++ b/board/nvidia/dts/tegra20-ventana.dts @@ -14,19 +14,6 @@ reg = <0x00000000 0x40000000>; }; - clocks { - clk_32k: clk_32k { - clock-frequency = <32000>; - }; - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006300 { clock-frequency = < 216000000 >; }; diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index f830cf3995d..4579557d6d1 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -16,16 +16,6 @@ reg = < 0x00000000 0x20000000 >; }; - clocks { - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - serial@70006000 { clock-frequency = < 216000000 >; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 60b91b4d175..3223ed4c21b 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -20,19 +20,6 @@ reg = <0x80000000 0x40000000>; }; - clocks { - clk_32k: clk_32K { - clock-frequency = <32768>; - }; - osc { - clock-frequency = <12000000>; - }; - }; - - clock@60006000 { - clocks = <&clk_32k &osc>; - }; - i2c@7000c000 { clock-frequency = <100000>; }; |