Merge branch 'master' into next

Signed-off-by: Tom Rini <trini@konsulko.com>

53 files changed, 4655 insertions, 171 deletions

diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c
index aa4e29b1560..a29fe362317 100644
--- a/board/CZ.NIC/turris_atsha_otp.c
+++ b/board/CZ.NIC/turris_atsha_otp.c
@@ -93,30 +93,57 @@ int turris_atsha_otp_init_mac_addresses(int first_idx)
 	return 0;
 }
 
-int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num)
+int turris_atsha_otp_init_serial_number(void)
+{
+	char serial[17];
+	int ret;
+
+	ret = turris_atsha_otp_get_serial_number(serial);
+	if (ret)
+		return ret;
+
+	if (!env_get("serial#"))
+		return -1;
+
+	return 0;
+}
+
+int turris_atsha_otp_get_serial_number(char serial[17])
 {
 	struct udevice *dev = get_atsha204a_dev();
+	u32 version_num, serial_num;
+	const char *serial_env;
 	int ret;
 
 	if (!dev)
 		return -1;
 
+	serial_env = env_get("serial#");
+	if (serial_env && strlen(serial_env) == 16) {
+		memcpy(serial, serial_env, 17);
+		return 0;
+	}
+
 	ret = atsha204a_wakeup(dev);
 	if (ret)
 		return ret;
 
 	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 			     TURRIS_ATSHA_OTP_VERSION,
-			     (u8 *)version_num);
+			     (u8 *)&version_num);
 	if (ret)
 		return ret;
 
 	ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
 			     TURRIS_ATSHA_OTP_SERIAL,
-			     (u8 *)serial_num);
+			     (u8 *)&serial_num);
 	if (ret)
 		return ret;
 
 	atsha204a_sleep(dev);
+
+	sprintf(serial, "%08X%08X", be32_to_cpu(version_num), be32_to_cpu(serial_num));
+	env_set("serial#", serial);
+
 	return 0;
 }
diff --git a/board/CZ.NIC/turris_atsha_otp.h b/board/CZ.NIC/turris_atsha_otp.h
index bd4308fdc3e..2cfe20bbc3a 100644
--- a/board/CZ.NIC/turris_atsha_otp.h
+++ b/board/CZ.NIC/turris_atsha_otp.h
@@ -4,6 +4,7 @@
 #define TURRIS_ATSHA_OTP_H
 
 int turris_atsha_otp_init_mac_addresses(int first_idx);
-int turris_atsha_otp_get_serial_number(u32 *version_num, u32 *serial_num);
+int turris_atsha_otp_init_serial_number(void);
+int turris_atsha_otp_get_serial_number(char serial[17]);
 
 #endif
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 3dbd68e5236..ff1c4cb1707 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -23,6 +23,7 @@
 #include <linux/string.h>
 #include <miiphy.h>
 #include <spi.h>
+#include <spi_flash.h>
 
 #include "mox_sp.h"
 
@@ -339,6 +340,51 @@ static int get_reset_gpio(struct gpio_desc *reset_gpio)
 	return 0;
 }
 
+/* Load default system DTB binary to $fdr_addr */
+static void load_spi_dtb(void)
+{
+	const char *const env_name[1] = { "fdt_addr" };
+	unsigned long size, offset;
+	struct udevice *spi_dev;
+	struct spi_flash *flash;
+	const char *addr_str;
+	unsigned long addr;
+	void *buf;
+
+	addr_str = env_get(env_name[0]);
+	if (!addr_str) {
+		env_set_default_vars(1, (char * const *)env_name, 0);
+		addr_str = env_get(env_name[0]);
+	}
+
+	if (!addr_str)
+		return;
+
+	addr = hextoul(addr_str, NULL);
+	if (!addr)
+		return;
+
+	spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, &spi_dev);
+	flash = dev_get_uclass_priv(spi_dev);
+	if (!flash)
+		return;
+
+	/*
+	 * SPI NOR "dtb" partition offset & size hardcoded for now because the
+	 * mtd subsystem does not offer finding the partition yet and we do not
+	 * want to reimplement OF partition parser here.
+	 */
+	offset = 0x7f0000;
+	size = 0x10000;
+
+	buf = map_physmem(addr, size, MAP_WRBACK);
+	if (!buf)
+		return;
+
+	spi_flash_read(flash, offset, size, buf);
+	unmap_physmem(buf, size);
+}
+
 int misc_init_r(void)
 {
 	u8 mac[2][6];
@@ -358,6 +404,8 @@ int misc_init_r(void)
 			eth_env_set_enetaddr_by_index("eth", i, mac[i]);
 	}
 
+	load_spi_dtb();
+
 	return 0;
 }
 
@@ -440,8 +488,9 @@ static void handle_reset_button(void)
 	env_set_default_vars(1, (char * const *)vars, 0);
 
 	if (read_reset_button()) {
-		const char * const vars[2] = {
+		const char * const vars[3] = {
 			"bootcmd",
+			"bootdelay",
 			"distro_bootcmd",
 		};
 
@@ -449,7 +498,7 @@ static void handle_reset_button(void)
 		 * Set the above envs to their default values, in case the user
 		 * managed to break them.
 		 */
-		env_set_default_vars(2, (char * const *)vars, 0);
+		env_set_default_vars(3, (char * const *)vars, 0);
 
 		/* Ensure bootcmd_rescue is used by distroboot */
 		env_set("boot_targets", "rescue");
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index ab5061ef582..19c5043fcba 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -549,8 +549,9 @@ static void handle_reset_button(void)
 	env_set_ulong("omnia_reset", reset_status);
 
 	if (reset_status) {
-		const char * const vars[2] = {
+		const char * const vars[3] = {
 			"bootcmd",
+			"bootdelay",
 			"distro_bootcmd",
 		};
 
@@ -558,7 +559,7 @@ static void handle_reset_button(void)
 		 * Set the above envs to their default values, in case the user
 		 * managed to break them.
 		 */
-		env_set_default_vars(2, (char * const *)vars, 0);
+		env_set_default_vars(3, (char * const *)vars, 0);
 
 		/* Ensure bootcmd_rescue is used by distroboot */
 		env_set("boot_targets", "rescue");
@@ -653,7 +654,7 @@ static void initialize_switch(void)
 	ctrl[1] = EXT_CTL_nRES_LAN;
 	err = omnia_mcu_write(CMD_EXT_CONTROL, ctrl, sizeof(ctrl));
 
-	mdelay(10);
+	mdelay(50);
 
 	/* Change RGMII pins back to RGMII mode */
 
@@ -963,19 +964,15 @@ int board_late_init(void)
 
 int show_board_info(void)
 {
-	u32 version_num, serial_num;
+	char serial[17];
 	int err;
 
-	err = turris_atsha_otp_get_serial_number(&version_num, &serial_num);
+	err = turris_atsha_otp_get_serial_number(serial);
 	printf("Model: Turris Omnia\n");
 	printf("  MCU type: %s\n", omnia_get_mcu_type());
 	printf("  MCU version: %s\n", omnia_get_mcu_version());
 	printf("  RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
-	if (err)
-		printf("  Serial Number: unknown\n");
-	else
-		printf("  Serial Number: %08X%08X\n", be32_to_cpu(version_num),
-		       be32_to_cpu(serial_num));
+	printf("  Serial Number: %s\n", !err ? serial : "unknown");
 
 	return 0;
 }
@@ -983,6 +980,7 @@ int show_board_info(void)
 int misc_init_r(void)
 {
 	turris_atsha_otp_init_mac_addresses(1);
+	turris_atsha_otp_init_serial_number();
 	return 0;
 }
 
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index 3e5e0a0b5c6..c6ecc323bb9 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -132,6 +132,8 @@ int board_late_init(void)
 		dev = mmc_dev->dev;
 		device_remove(dev, DM_REMOVE_NORMAL);
 		device_unbind(dev);
+		if (of_live_active())
+			ofnode_set_enabled(dev_ofnode(dev), false);
 	}
 
 	/* Ensure that 'env default -a' set correct value to $fdtfile */
diff --git a/board/bsh/imx6ulz_smm_m2/Kconfig b/board/bsh/imx6ulz_smm_m2/Kconfig
new file mode 100644
index 00000000000..e38df7ce5cb
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6ULZ_SMM_M2
+
+config SYS_BOARD
+	default "imx6ulz_smm_m2"
+
+config SYS_VENDOR
+	default "bsh"
+
+config SYS_CONFIG_NAME
+	default "imx6ulz_smm_m2"
+
+endif
diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS
new file mode 100644
index 00000000000..8f3d79dbb84
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6ULZ_SMM_M2 BOARD
+M:	Michael Trimarchi <michael@amarulasolutions.com>
+S:	Maintained
+F:	board/bsh/mx6ulz_smm_m2/
+F:	include/configs/imx6ulz_smm_m2.h
+F:	configs/imx6ulz_smm_m2_defconfig
diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile
new file mode 100644
index 00000000000..b761bbb2f90
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2021 Amarula Solutions B.V.
+
+obj-y  := imx6ulz_smm_m2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+
diff --git a/board/bsh/imx6ulz_smm_m2/README b/board/bsh/imx6ulz_smm_m2/README
new file mode 100644
index 00000000000..03d01325a97
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/README
@@ -0,0 +1,67 @@
+How to Update U-Boot on imx6ulz_smm_m2 board
+--------------------------------------------
+
+Required software on the host PC:
+
+- UUU: https://github.com/NXPmicro/mfgtools
+
+Build U-Boot for m2:
+
+$ make mrproper
+$ make imx6ulz_smm_m2_defconfig
+$ make
+
+This generates the SPL and u-boot-dtb.img binaries.
+
+1. Loading U-Boot via USB Serial Download Protocol
+
+Copy SPL and u-boot-dtb.img to the uuu folder.
+
+Load the U-Boot via USB:
+
+$ sudo uuu -v -b nand_script.lst u-boot-with-spl.imx
+
+where nand_script.lst contains the following:
+
+uuu_version 1.2.39
+
+# @_flash.bin            | bootloader
+# @_image   [_flash.bin] | image burn to nand, default is the same as bootloader
+
+# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ
+SDP: boot -f _flash.bin
+
+# This command will be run when ROM support stream mode
+# i.MX8QXP, i.MX8QM
+SDPS: boot -f _flash.bin
+
+# These commands will be run when use SPL and will be skipped if no spl
+# SDPU will be deprecated. please use SDPV instead of SDPU
+# {
+SDPU: delay 1000
+SDPU: write -f _flash.bin -offset 0x57c00
+SDPU: jump
+# }
+
+# These commands will be run when use SPL and will be skipped if no spl
+# if (SPL support SDPV)
+# {
+SDPV: delay 1000
+SDPV: write -f _flash.bin -offset 0x11000
+SDPV: jump
+# }
+
+FB: ucmd setenv fastboot_buffer ${loadaddr}
+FB: download -f _image
+FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi
+# Burn image to nandfit partition if needed
+FB: ucmd if env exists nandfit_part; then nand erase.part nandfit; nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true; fi;
+FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes}
+FB: Done
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
diff --git a/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c
new file mode 100644
index 00000000000..c82eabbfbea
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (C) 2021 BSH Hausgeraete GmbH
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <common.h>
+#include <env.h>
+#include <linux/sizes.h>
+
+static void setup_gpmi_nand(void)
+{
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			   MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			   MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+};
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_gpmi_nand();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (is_boot_from_usb()) {
+		env_set("bootcmd", "run bootcmd_mfg");
+		env_set("bootdelay", "0");
+	}
+
+	return 0;
+}
diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c
new file mode 100644
index 00000000000..5b4812e129e
--- /dev/null
+++ b/board/bsh/imx6ulz_smm_m2/spl.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ull_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <linux/libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+		       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+		       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t uart4_pads[] = {
+	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds		= 0x00000028,
+	.grp_ddrmode_ctl	= 0x00020000,
+	.grp_b0ds		= 0x00000028,
+	.grp_ctlds		= 0x00000028,
+	.grp_b1ds		= 0x00000028,
+	.grp_ddrpke		= 0x00000000,
+	.grp_ddrmode		= 0x00020000,
+	.grp_ddr_type		= 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0		= 0x00000028,
+	.dram_dqm1		= 0x00000028,
+	.dram_ras		= 0x00000028,
+	.dram_cas		= 0x00000028,
+	.dram_odt0		= 0x00000028,
+	.dram_odt1		= 0x00000028,
+	.dram_sdba2		= 0x00000000,
+	.dram_sdclk_0		= 0x00000028,
+	.dram_sdqs0		= 0x00000028,
+	.dram_sdqs1		= 0x00000028,
+	.dram_reset		= 0x000c0028,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0		= 0x00000000,
+	.p0_mpwldectrl1		= 0x00100010,
+	.p0_mpdgctrl0		= 0x414c014c,
+	.p0_mpdgctrl1		= 0x00000000,
+	.p0_mprddlctl		= 0x40403a42,
+	.p0_mpwrdlctl		= 0x4040342e,
+};
+
+static struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize			= 0,
+	.cs1_mirror		= 0,
+	.cs_density		= 32,
+	.ncs			= 1,
+	.bi_on			= 1,
+	.rtt_nom		= 1,
+	.rtt_wr			= 0,
+	.ralat			= 5,
+	.walat			= 1,
+	.mif3_mode		= 3,
+	.rst_to_cke		= 0x23,	/* 33 cycles (JEDEC value for DDR3) - total of 500 us */
+	.sde_to_rst		= 0x10,	/* 14 cycles (JEDEC value for DDR3) - total of 200 us */
+	.refsel			= 1,
+	.refr			= 3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed		= 1333,
+	.density		= 2,
+	.width			= 16,
+	.banks			= 8,
+	.rowaddr		= 13,
+	.coladdr		= 10,
+	.pagesz			= 2,
+	.trcd			= 1350,
+	.trcmin			= 4950,
+	.trasmin		= 3600,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void imx6ul_spl_dram_cfg(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+	arch_cpu_init();
+	timer_init();
+	setup_iomux_uart();
+	preloader_console_init();
+	imx6ul_spl_dram_cfg();
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
index c2abcb54895..f40fd48fc49 100644
--- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
+++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
@@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4000d4, 0x940000 },
 	{ 0x3d4000dc, 0xd4002d },
 	{ 0x3d4000e0, 0x310000 },
-	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000e8, 0x36004d },
 	{ 0x3d4000ec, 0x16004d },
 	{ 0x3d400100, 0x191e1920 },
 	{ 0x3d400104, 0x60630 },
@@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
 	{ 0x3d400250, 0x29001701 },
 	{ 0x3d400254, 0x2c },
 	{ 0x3d40025c, 0x4000030 },
@@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d402064, 0xc001c },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
-	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020e8, 0x36004d },
 	{ 0x3d4020ec, 0x16004d },
 	{ 0x3d402100, 0xa040305 },
 	{ 0x3d402104, 0x30407 },
@@ -97,7 +98,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d403064, 0x30007 },
 	{ 0x3d4030dc, 0x840000 },
 	{ 0x3d4030e0, 0x310000 },
-	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030e8, 0x36004d },
 	{ 0x3d4030ec, 0x16004d },
 	{ 0x3d403100, 0xa010102 },
 	{ 0x3d403104, 0x30404 },
@@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
 	{ 0x54039, 0x3100 },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1137,25 +1138,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
 	{ 0x54039, 0x3100 },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1177,25 +1178,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54012, 0x110 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1692,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0x400d6, 0x20a },
 	{ 0x400d7, 0x20b },
 	{ 0x2003a, 0x2 },
-	{ 0x2000b, 0x5d },
+	{ 0x2000b, 0x34b },
 	{ 0x2000c, 0xbb },
 	{ 0x2000d, 0x753 },
 	{ 0x2000e, 0x2c },
-	{ 0x12000b, 0xc },
+	{ 0x12000b, 0x70 },
 	{ 0x12000c, 0x19 },
 	{ 0x12000d, 0xfa },
 	{ 0x12000e, 0x10 },
-	{ 0x22000b, 0x3 },
+	{ 0x22000b, 0x1c },
 	{ 0x22000c, 0x6 },
 	{ 0x22000d, 0x3e },
 	{ 0x22000e, 0x10 },
diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
index e44c1ea2772..0e5be8efd00 100644
--- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
+++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
@@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4000d4, 0x940000 },
 	{ 0x3d4000dc, 0xd4002d },
 	{ 0x3d4000e0, 0x310000 },
-	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000e8, 0x36004d },
 	{ 0x3d4000ec, 0x16004d },
 	{ 0x3d400100, 0x191e1920 },
 	{ 0x3d400104, 0x60630 },
@@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d400204, 0x80808 },
 	{ 0x3d400214, 0x7070707 },
 	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
 	{ 0x3d400250, 0x29001701 },
 	{ 0x3d400254, 0x2c },
 	{ 0x3d40025c, 0x4000030 },
@@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d402064, 0xc001c },
 	{ 0x3d4020dc, 0x840000 },
 	{ 0x3d4020e0, 0x310000 },
-	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020e8, 0x36004d },
 	{ 0x3d4020ec, 0x16004d },
 	{ 0x3d402100, 0xa040305 },
 	{ 0x3d402104, 0x30407 },
@@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54012, 0x310 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0x54012, 0x310 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
 	{ 0x54039, 0x3100 },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1172,31 +1173,30 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400d, 0x100 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
-	{ 0x5401b, 0x4d66 },
+	{ 0x5401b, 0x4d36 },
 	{ 0x5401c, 0x4d00 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
-	{ 0x54021, 0x4d66 },
+	{ 0x54021, 0x4d36 },
 	{ 0x54022, 0x4d00 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
-	{ 0x54034, 0x6600 },
+	{ 0x54034, 0x3600 },
 	{ 0x54035, 0x4d },
 	{ 0x54036, 0x4d },
 	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
 	{ 0x54039, 0x312d },
-	{ 0x5403a, 0x6600 },
+	{ 0x5403a, 0x3600 },
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
@@ -1693,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0x400d6, 0x20a },
 	{ 0x400d7, 0x20b },
 	{ 0x2003a, 0x2 },
-	{ 0x2000b, 0x5d },
+	{ 0x2000b, 0x34b },
 	{ 0x2000c, 0xbb },
 	{ 0x2000d, 0x753 },
 	{ 0x2000e, 0x2c },
-	{ 0x12000b, 0xc },
+	{ 0x12000b, 0x70 },
 	{ 0x12000c, 0x19 },
 	{ 0x12000d, 0xfa },
 	{ 0x12000e, 0x10 },
-	{ 0x22000b, 0x3 },
+	{ 0x22000b, 0x1c },
 	{ 0x22000c, 0x6 },
 	{ 0x22000d, 0x3e },
 	{ 0x22000e, 0x10 },
@@ -1715,6 +1715,10 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0x90013, 0x6152 },
 	{ 0x20010, 0x5a },
 	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
 	{ 0x40080, 0xe0 },
 	{ 0x40081, 0x12 },
 	{ 0x40082, 0xe0 },
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
index 2eda4a59569..a4c1b121c27 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
@@ -1799,8 +1799,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	{
-		/* P0 3732mts 1D */
-		.drate = 3732,
+		/* P0 3733mts 1D */
+		.drate = 3733,
 		.fw_type = FW_1D_IMAGE,
 		.fsp_cfg = ddr_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1820,8 +1820,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
 	},
 	{
-		/* P0 3732mts 2D */
-		.drate = 3732,
+		/* P0 3733mts 2D */
+		.drate = 3733,
 		.fw_type = FW_2D_IMAGE,
 		.fsp_cfg = ddr_fsp0_2d_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1840,5 +1840,5 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {
 	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
 	.ddrphy_pie = ddr_phy_pie,
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-	.fsp_table = { 3732, 400, 100, },
+	.fsp_table = { 3733, 400, 100, },
 };
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 7e4f3ff157f..2bc0d7b943a 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -527,56 +527,6 @@ static void sysconf_init(void)
 #endif
 }
 
-static void board_init_fmc2(void)
-{
-#define STM32_FMC2_BCR1			0x0
-#define STM32_FMC2_BTR1			0x4
-#define STM32_FMC2_BWTR1		0x104
-#define STM32_FMC2_BCR(x)		((x) * 0x8 + STM32_FMC2_BCR1)
-#define STM32_FMC2_BCRx_FMCEN		BIT(31)
-#define STM32_FMC2_BCRx_WREN		BIT(12)
-#define STM32_FMC2_BCRx_RSVD		BIT(7)
-#define STM32_FMC2_BCRx_FACCEN		BIT(6)
-#define STM32_FMC2_BCRx_MWID(n)		((n) << 4)
-#define STM32_FMC2_BCRx_MTYP(n)		((n) << 2)
-#define STM32_FMC2_BCRx_MUXEN		BIT(1)
-#define STM32_FMC2_BCRx_MBKEN		BIT(0)
-#define STM32_FMC2_BTR(x)		((x) * 0x8 + STM32_FMC2_BTR1)
-#define STM32_FMC2_BTRx_DATAHLD(n)	((n) << 30)
-#define STM32_FMC2_BTRx_BUSTURN(n)	((n) << 16)
-#define STM32_FMC2_BTRx_DATAST(n)	((n) << 8)
-#define STM32_FMC2_BTRx_ADDHLD(n)	((n) << 4)
-#define STM32_FMC2_BTRx_ADDSET(n)	((n) << 0)
-
-#define RCC_MP_AHB6RSTCLRR		0x218
-#define RCC_MP_AHB6RSTCLRR_FMCRST	BIT(12)
-#define RCC_MP_AHB6ENSETR		0x19c
-#define RCC_MP_AHB6ENSETR_FMCEN		BIT(12)
-
-	const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
-			STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
-			STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
-			STM32_FMC2_BCRx_MBKEN;
-	const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
-			STM32_FMC2_BTRx_BUSTURN(2) |
-			STM32_FMC2_BTRx_DATAST(0x22) |
-			STM32_FMC2_BTRx_ADDHLD(2) |
-			STM32_FMC2_BTRx_ADDSET(2);
-
-	/* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
-	writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
-	writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
-
-	/* KS8851-16MLL -- Muxed mode */
-	writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
-	writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
-	/* AS7C34098 SRAM on X11 -- Muxed mode */
-	writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
-	writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
-
-	setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
-}
-
 #ifdef CONFIG_DM_REGULATOR
 #define STPMIC_NVM_BUCKS_VOUT_SHR			0xfc
 #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2		0
@@ -671,8 +621,6 @@ int board_init(void)
 
 	sysconf_init();
 
-	board_init_fmc2();
-
 	return 0;
 }
 
diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
index 28dcc2a6903..bdf3cc03dc5 100644
--- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c
+++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -70,7 +70,7 @@ int rockchip_dnl_key_pressed(void)
 {
 	unsigned int val;
 
-	if (adc_channel_single_shot("saradc", 1, &val)) {
+	if (adc_channel_single_shot("saradc@ff1e0000", 1, &val)) {
 		printf("%s read adc key val failed\n", __func__);
 		return false;
 	}
diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig
new file mode 100644
index 00000000000..c61fc579713
--- /dev/null
+++ b/board/freescale/imxrt1170-evk/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_IMXRT1170_EVK
+
+config SYS_BOARD
+	string
+	default "imxrt1170-evk"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "imxrt1170"
+
+config SYS_CONFIG_NAME
+	string
+	default "imxrt1170-evk"
+
+config IMX_CONFIG
+	default "board/freescale/imxrt1170-evk/imximage.cfg"
+
+endif
diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS
new file mode 100644
index 00000000000..1fc3179c005
--- /dev/null
+++ b/board/freescale/imxrt1170-evk/MAINTAINERS
@@ -0,0 +1,7 @@
+IMXRT1170 EVALUATION KIT
+M:	Giulio Benetti <giulio.benetti@benettiengineering.com>
+M:	Jesse Taube <Mr.Bossman075@gmail.com>
+S:	Maintained
+F:	board/freescale/imxrt1170-evk
+F:	include/configs/imxrt1170-evk.h
+F:	configs/imxrt1170-evk_defconfig
diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile
new file mode 100644
index 00000000000..857a168b09d
--- /dev/null
+++ b/board/freescale/imxrt1170-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y	:= imxrt1170-evk.o
diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg
new file mode 100644
index 00000000000..57583d04ce6
--- /dev/null
+++ b/board/freescale/imxrt1170-evk/imximage.cfg
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ * Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt1170-evk/imxrt1170-evk.c
new file mode 100644
index 00000000000..4b82ee5e9ce
--- /dev/null
+++ b/board/freescale/imxrt1170-evk/imxrt1170-evk.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+#endif
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	debug("SPL: booting kernel\n");
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+	struct udevice *dev;
+	int rv;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv)
+		debug("DRAM init failed: %d\n", rv);
+	return rv;
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+	spl_dram_init();
+	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 08b43ff5e4c..4d2fce38412 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -114,7 +114,7 @@ dimm_params_t ddr_raw_timing = {
 	.mirrored_dimm = 0,
 	.n_row_addr = 15,
 	.n_col_addr = 10,
-	.bank_addr_bits = 0,
+	.bank_addr_bits = 2,
 	.bank_group_bits = 2,
 	.edc_config = 0,
 	.burst_lengths_bitmask = 0x0c,
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
index 86ff04e69d9..f542decec79 100644
--- a/board/freescale/p1_p2_rdb_pc/README
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -60,5 +60,5 @@ enabled in relative defconfig file,
    CONFIG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
+1. use 'u-boot.bin' for NOR boot.
 2. use 'u-boot-with-spl.bin' for other boot.
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a71952dcf39..b301491ef81 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -83,7 +83,19 @@ struct cpld_data {
 #define CPLD_FXS_LED	0x0F
 #define CPLD_SYS_RST	0x00
 
-void board_reset(void)
+void board_reset_prepare(void)
+{
+	/*
+	 * During reset preparation, turn off external watchdog.
+	 * This ensures that external watchdog does not trigger
+	 * another reset or possible infinite reset loop.
+	 */
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
+	in_8(&cpld_data->wd_cfg); /* Read back to sync write */
+}
+
+void board_reset_last(void)
 {
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	out_8(&cpld_data->system_rst, 1);
@@ -92,12 +104,46 @@ void board_reset(void)
 void board_cpld_init(void)
 {
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+	u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg);
 
 	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
 	out_8(&cpld_data->status_led, CPLD_STATUS_LED);
 	out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
 	out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
+
+	/*
+	 * CPLD's system reset register on P1/P2 RDB boards is not autocleared
+	 * after flipping it. If this register is set to one then CPLD triggers
+	 * reset of CPU in few ms.
+	 *
+	 * CPLD does not trigger reset of CPU for 100ms after the last reset.
+	 *
+	 * This means that trying to reset board via CPLD system reset register
+	 * cause reboot loop. To prevent this reboot loop, the only workaround
+	 * is to try to clear CPLD's system reset register as early as possible
+	 * and it has to be done in 100ms since the last start of reset.
+	 */
 	out_8(&cpld_data->system_rst, CPLD_SYS_RST);
+
+	/*
+	 * If watchdog timer was already set to non-disabled value then it means
+	 * that watchdog timer was already activated, has already expired and
+	 * caused CPU reset. If this happened then due to CPLD firmware bug,
+	 * writing to wd_cfg register has no effect and therefore it is not
+	 * possible to reactivate watchdog timer again. Also if CPU was reset
+	 * via watchdog then some peripherals like i2c do not work. Watchdog and
+	 * i2c start working again after CPU reset via non-watchdog method.
+	 *
+	 * So in case watchdog timer register in CPLD was already enabled then
+	 * disable it in CPLD and reset CPU which cause new boot. Watchdog timer
+	 * is disabled few lines above, after reading CPLD previous value.
+	 * This logic (disabling timer before reset) prevents reboot loop.
+	 */
+	if (prev_wd_cfg != CPLD_WD_CFG) {
+		eieio();
+		do_reset(NULL, 0, 0, NULL);
+		while (1); /* do_reset() does not occur immediately */
+	}
 }
 
 void board_gpio_init(void)
@@ -368,6 +414,24 @@ int board_eth_init(struct bd_info *bis)
 }
 #endif
 
+#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP)
+static void fix_max6370_watchdog(void *blob)
+{
+	int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370");
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 gpioval = in_be32(&pgpio->gpdat);
+
+	/*
+	 * Delete watchdog max6370 node in load_default mode (detected by
+	 * GPIO7 - LOAD_DEFAULT_N) because CPLD in load_default mode ignores
+	 * watchdog reset signal. CPLD in load_default mode does not reset
+	 * board when watchdog triggers reset signal.
+	 */
+	if (!(gpioval & BIT(31-7)) && off >= 0)
+		fdt_del_node(blob, off);
+}
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
@@ -393,6 +457,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 			sizeof("okay"), 0);
 #endif
 
+	fix_max6370_watchdog(blob);
+
 #if defined(CONFIG_HAS_FSL_DR_USB)
 	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
@@ -444,3 +510,11 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *blob)
+{
+	fix_max6370_watchdog(blob);
+	return 0;
+}
+#endif
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index b60027ebd9a..eda84bf2b1f 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -31,6 +31,12 @@ void board_init_f(ulong bootflag)
 	u32 plat_ratio, bus_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
+	/*
+	 * Call board_early_init_f() as early as possible as it workarounds
+	 * reboot loop due to broken CPLD state machine for reset line.
+	 */
+	board_early_init_f();
+
 	console_init_f();
 
 	/* Set pmuxcr to allow both i2c1 and i2c2 */
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 105d9e38aac..65cedd42a0d 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 5, BOOKE_PAGESZ_1M, 1),
 #endif
+#endif /* not SPL */
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
-#endif /* not SPL */
 
 #ifdef CONFIG_SYS_NAND_BASE
 	/* *I*G - NAND */
diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README
index 79f77e49612..96612daeeb1 100644
--- a/board/freescale/p2041rdb/README
+++ b/board/freescale/p2041rdb/README
@@ -100,9 +100,6 @@ enabled in relative defconfig file,
 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
    CONFIG_RESET_VECTOR_ADDRESS - 0xffc
 
-If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
-instead of u-boot.bin for all boot.
-
 CPLD command
 ============
 The CPLD is used to control the power sequence and some serdes lane
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index 84deb9562a1..de170f52b4d 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -267,7 +267,7 @@ enabled in relative defconfig file,
    config_reset_vector_address - 0xffc
 
 if device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for nor boot.
+1. use 'u-boot.bin' for nor boot.
 2. use 'u-boot-with-spl-pbl.bin' for other boot.
 
 2-stage NAND/SPI/SD boot loader
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index 09cb98e33d6..e90dca41663 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -382,5 +382,5 @@ enabled in relative defconfig file,
    CONFIG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
+1. use 'u-boot.bin' for NOR boot.
 2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
index 75d317342f6..63953d6b9b6 100755
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@@ -288,5 +288,5 @@ enabled in relative defconfig file,
    CONFIG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
+1. use 'u-boot.bin' for NOR boot.
 2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index c4bfd3b466f..60551f6723e 100644
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -284,5 +284,5 @@ enabled in relative defconfig file,
    CONFIG_RESET_VECTOR_ADDRESS - 0xffc
 
 If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
+1. use 'u-boot.bin' for NOR boot.
 2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c
index 7a46f44828c..ac52cc0a9ec 100644
--- a/board/gateworks/venice/eeprom.c
+++ b/board/gateworks/venice/eeprom.c
@@ -20,6 +20,7 @@
 struct venice_board_info som_info;
 struct venice_board_info base_info;
 char venice_model[32];
+char venice_baseboard_model[32];
 u32 venice_serial;
 
 /* return a mac address from EEPROM info */
@@ -321,6 +322,7 @@ int eeprom_init(int quiet)
 			base_info.model[3], /* baseboard */
 			base_info.model[4], base_info.model[5], /* subload of baseboard */
 			som_info.model[4], som_info.model[5]); /* last 2digits of SOM */
+		strlcpy(venice_baseboard_model, base_info.model, sizeof(venice_baseboard_model));
 
 		/* baseboard revision */
 		rev_pcb = get_pcb_rev(base_info.model);
@@ -357,6 +359,11 @@ const char *eeprom_get_model(void)
 	return venice_model;
 }
 
+const char *eeprom_get_baseboard_model(void)
+{
+	return venice_baseboard_model;
+}
+
 u32 eeprom_get_serial(void)
 {
 	return venice_serial;
diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h
index 37bfe76ad81..8ea7318d7df 100644
--- a/board/gateworks/venice/eeprom.h
+++ b/board/gateworks/venice/eeprom.h
@@ -26,8 +26,11 @@ struct venice_board_info {
 
 int eeprom_init(int quiet);
 const char *eeprom_get_model(void);
+const char *eeprom_get_baseboard_model(void);
 const char *eeprom_get_dtb_name(int level, char *buf, int len);
 int eeprom_getmac(int index, uint8_t *enetaddr);
 uint32_t eeprom_get_serial(void);
+int get_bom_rev(const char *str);
+char get_pcb_rev(const char *str);
 
 #endif
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index f1efabb203d..32b25ffd3ed 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -3,6 +3,7 @@
  * Copyright 2021 Gateworks Corporation
  */
 
+#include <fdt_support.h>
 #include <init.h>
 #include <led.h>
 #include <miiphy.h>
@@ -169,26 +170,54 @@ int board_mmc_get_env_dev(int devno)
 	return devno;
 }
 
-int ft_board_setup(void *blob, struct bd_info *bd)
+int ft_board_setup(void *fdt, struct bd_info *bd)
 {
+	const char *base_model = eeprom_get_baseboard_model();
+	char pcbrev;
 	int off;
 
 	/* set board model dt prop */
-	fdt_setprop_string(blob, 0, "board", eeprom_get_model());
+	fdt_setprop_string(fdt, 0, "board", eeprom_get_model());
 
 	/* update temp thresholds */
-	off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
+	off = fdt_path_offset(fdt, "/thermal-zones/cpu-thermal/trips");
 	if (off >= 0) {
 		int minc, maxc, prop;
 
 		get_cpu_temp_grade(&minc, &maxc);
-		fdt_for_each_subnode(prop, blob, off) {
-			const char *type = fdt_getprop(blob, prop, "type", NULL);
+		fdt_for_each_subnode(prop, fdt, off) {
+			const char *type = fdt_getprop(fdt, prop, "type", NULL);
 
 			if (type && (!strcmp("critical", type)))
-				fdt_setprop_u32(blob, prop, "temperature", maxc * 1000);
+				fdt_setprop_u32(fdt, prop, "temperature", maxc * 1000);
 			else if (type && (!strcmp("passive", type)))
-				fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000);
+				fdt_setprop_u32(fdt, prop, "temperature", (maxc - 10) * 1000);
+		}
+	}
+
+	if (!strncmp(base_model, "GW73", 4)) {
+		pcbrev = get_pcb_rev(base_model);
+
+		if (pcbrev > 'B') {
+			printf("adjusting dt for %s\n", base_model);
+
+			/*
+			 * revC replaced PCIe 5-port switch with 4-port
+			 * which changed ethernet1 PCIe GbE
+			 * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
+			 *   to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
+			 */
+			off = fdt_path_offset(fdt, "ethernet1");
+			if (off > 0) {
+				u32 reg[5];
+
+				fdt_set_name(fdt, off, "pcie@5,0");
+				off = fdt_parent_offset(fdt, off);
+				fdt_set_name(fdt, off, "pcie@2,3");
+				memset(reg, 0, sizeof(reg));
+				reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0));
+				fdt_setprop(fdt, off, "reg", reg, sizeof(reg));
+			}
 		}
 	}
 
diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c
index 33c6843c3f7..331de29baee 100644
--- a/board/kontron/sl28/common.c
+++ b/board/kontron/sl28/common.c
@@ -2,6 +2,9 @@
 
 #include <common.h>
 #include <asm/global_data.h>
+#include <asm/io.h>
+
+#include "sl28.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -9,3 +12,22 @@ u32 get_lpuart_clk(void)
 {
 	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
 }
+
+enum boot_source sl28_boot_source(void)
+{
+	u32 rcw_src = in_le32(DCFG_BASE + DCFG_PORSR1) & DCFG_PORSR1_RCW_SRC;
+
+	switch (rcw_src) {
+	case DCFG_PORSR1_RCW_SRC_SDHC1:
+		return BOOT_SOURCE_SDHC;
+	case DCFG_PORSR1_RCW_SRC_SDHC2:
+		return BOOT_SOURCE_MMC;
+	case DCFG_PORSR1_RCW_SRC_I2C:
+		return BOOT_SOURCE_I2C;
+	case DCFG_PORSR1_RCW_SRC_FSPI_NOR:
+		return BOOT_SOURCE_SPI;
+	default:
+		debug("unknown bootsource (%08x)\n", rcw_src);
+		return BOOT_SOURCE_UNKNOWN;
+	}
+}
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index 32e9694b77c..0576b3eae48 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -24,6 +24,8 @@
 #include <fdtdec.h>
 #include <miiphy.h>
 
+#include "sl28.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
@@ -60,6 +62,27 @@ int board_eth_init(struct bd_info *bis)
 	return pci_eth_init(bis);
 }
 
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	enum boot_source src = sl28_boot_source();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	if (!CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+		return ENVL_NOWHERE;
+
+	/* write and erase always operate on the environment */
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_SPI_FLASH;
+
+	/* failsafe boot will always use the compiled-in default environment */
+	if (src == BOOT_SOURCE_SPI)
+		return ENVL_NOWHERE;
+
+	return ENVL_SPI_FLASH;
+}
+
 static int __sl28cpld_read(uint reg)
 {
 	struct udevice *dev;
@@ -103,8 +126,28 @@ static void stop_recovery_watchdog(void)
 		wdt_stop(dev);
 }
 
+static void sl28_set_prompt(void)
+{
+	enum boot_source src = sl28_boot_source();
+
+	switch (src) {
+	case BOOT_SOURCE_SPI:
+		env_set("PS1", "[FAILSAFE] => ");
+		break;
+	case BOOT_SOURCE_SDHC:
+		env_set("PS1", "[SDHC] => ");
+		break;
+	default:
+		env_set("PS1", NULL);
+		break;
+	}
+}
+
 int fsl_board_late_init(void)
 {
+	if (IS_ENABLED(CONFIG_CMDLINE_PS_SUPPORT))
+		sl28_set_prompt();
+
 	/*
 	 * Usually, the after a board reset, the watchdog is enabled by
 	 * default. This is to supervise the bootloader boot-up. Therefore,
diff --git a/board/kontron/sl28/sl28.h b/board/kontron/sl28/sl28.h
new file mode 100644
index 00000000000..7f0105049cb
--- /dev/null
+++ b/board/kontron/sl28/sl28.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __SL28_H
+#define __SL28_H
+
+enum boot_source {
+	BOOT_SOURCE_UNKNOWN,
+	BOOT_SOURCE_SDHC,
+	BOOT_SOURCE_MMC,
+	BOOT_SOURCE_I2C,
+	BOOT_SOURCE_SPI,
+};
+
+enum boot_source sl28_boot_source(void);
+
+#endif
diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c
index 0e6ad5f37e1..ffaf517a8bb 100644
--- a/board/kontron/sl28/spl.c
+++ b/board/kontron/sl28/spl.c
@@ -5,6 +5,9 @@
 #include <asm/spl.h>
 #include <asm/arch-fsl-layerscape/fsl_serdes.h>
 #include <asm/arch-fsl-layerscape/soc.h>
+#include <spi_flash.h>
+
+#include "sl28.h"
 
 #define DCFG_RCWSR25 0x160
 #define GPINFO_HW_VARIANT_MASK 0xff
@@ -58,7 +61,56 @@ int board_fit_config_name_match(const char *name)
 
 void board_boot_order(u32 *spl_boot_list)
 {
-	spl_boot_list[0] = BOOT_DEVICE_SPI;
+	enum boot_source src = sl28_boot_source();
+
+	switch (src) {
+	case BOOT_SOURCE_SDHC:
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		break;
+	case BOOT_SOURCE_SPI:
+	case BOOT_SOURCE_I2C:
+		spl_boot_list[0] = BOOT_DEVICE_SPI;
+		break;
+	case BOOT_SOURCE_MMC:
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		break;
+	default:
+		panic("unexpected bootsource (%d)\n", src);
+		break;
+	}
+}
+
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
+{
+	enum boot_source src = sl28_boot_source();
+
+	switch (src) {
+	case BOOT_SOURCE_SPI:
+		return 0x000000;
+	case BOOT_SOURCE_I2C:
+		return 0x230000;
+	default:
+		panic("unexpected bootsource (%d)\n", src);
+		break;
+	}
+}
+
+const char *spl_board_loader_name(u32 boot_device)
+{
+	enum boot_source src = sl28_boot_source();
+
+	switch (src) {
+	case BOOT_SOURCE_SDHC:
+		return "SD card (Test mode)";
+	case BOOT_SOURCE_SPI:
+		return "Failsafe SPI flash";
+	case BOOT_SOURCE_I2C:
+		return "SPI flash";
+	case BOOT_SOURCE_MMC:
+		return "eMMC";
+	default:
+		return "(unknown)";
+	}
 }
 
 int board_early_init_f(void)
diff --git a/board/purism/librem5/Kconfig b/board/purism/librem5/Kconfig
new file mode 100644
index 00000000000..cf0f303683e
--- /dev/null
+++ b/board/purism/librem5/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LIBREM5
+
+config SYS_BOARD
+	default "librem5"
+
+config SYS_VENDOR
+	default "purism"
+
+config SYS_CONFIG_NAME
+	default "librem5"
+
+config IMX_CONFIG
+	default "board/purism/librem5/imximage-8mq-lpddr4.cfg"
+
+endif
diff --git a/board/purism/librem5/MAINTAINERS b/board/purism/librem5/MAINTAINERS
new file mode 100644
index 00000000000..09e7f20e33c
--- /dev/null
+++ b/board/purism/librem5/MAINTAINERS
@@ -0,0 +1,8 @@
+PURISM LIBREM5 PHONE
+M:	Angus Ainslie <angus@akkea.ca>
+R:	kernel@puri.sm
+S:	Supported
+F:	arch/arm/dts/imx8mq-librem5*
+F:	board/purism/librem5/
+F:	configs/librem5_defconfig
+F:	include/configs/librem5.h
diff --git a/board/purism/librem5/Makefile b/board/purism/librem5/Makefile
new file mode 100644
index 00000000000..47f25f047b7
--- /dev/null
+++ b/board/purism/librem5/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2017 NXP
+# Copyright 2019 Purism
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += librem5.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
+endif
diff --git a/board/purism/librem5/imximage-8mq-lpddr4.cfg b/board/purism/librem5/imximage-8mq-lpddr4.cfg
new file mode 100644
index 00000000000..3b5967105ba
--- /dev/null
+++ b/board/purism/librem5/imximage-8mq-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+FIT
+BOOT_FROM	sd
+SIGNED_HDMI     signed_hdmi.bin
+LOADER		u-boot-spl-ddr.bin	0x7E1000
diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c
new file mode 100644
index 00000000000..caa02655fc4
--- /dev/null
+++ b/board/purism/librem5/librem5.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2021 Purism
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/video.h>
+#include <fuse.h>
+#include <i2c.h>
+#include <spl.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <linux/delay.h>
+#include <linux/bitfield.h>
+#include <power/regulator.h>
+#include <usb/xhci.h>
+#include "librem5.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION)
+uint board_mmc_get_env_part(struct mmc *mmc)
+{
+	uint part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+
+	if (part == 7)
+		part = 0;
+	return part;
+}
+#endif
+
+int tps65982_wait_for_app(int timeout, int timeout_step)
+{
+	int ret;
+	char response[6];
+	struct udevice *udev, *bus;
+
+	log_debug("%s: starting\n", __func__);
+
+	/* Set the i2c bus */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
+	if (ret) {
+		log_err("%s: No bus %d\n", __func__, 0);
+		return 1;
+	}
+
+	ret = i2c_get_chip(bus, 0x3f, 1, &udev);
+	if (ret) {
+		log_err("%s: setting chip offset failed %d\n", __func__, ret);
+		return 1;
+	}
+
+	while (timeout > 0) {
+		ret = dm_i2c_read(udev, 0x03, (u8 *)response, 5);
+		log_debug("tps65982 mode %s\n", response);
+		if (response[1] == 'A')
+			return 0;
+		mdelay(timeout_step);
+		timeout -= timeout_step;
+		log_debug("tps65982 waited %d ms %c\n", timeout_step, response[1]);
+	}
+
+	return 1;
+}
+
+int tps65982_clear_dead_battery(void)
+{
+	int ret;
+	char cmd[5] = "\04DBfg";
+	struct udevice *udev, *bus;
+
+	log_debug("%s: starting\n", __func__);
+
+	/* Set the i2c bus */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
+	if (ret) {
+		log_err("%s: No bus %d\n", __func__, 0);
+		return 1;
+	}
+
+	ret = i2c_get_chip(bus, 0x3f, 1, &udev);
+	if (ret) {
+		log_err("%s: setting chip offset failed %d\n", __func__, ret);
+		return 1;
+	}
+
+	/* clearing the dead battery flag when not in dead battery condition
+	 * is a no-op, so there's no need to check if it's in effect
+	 */
+	ret = dm_i2c_write(udev, 0x08, cmd, 5);
+	if (ret) {
+		log_err("%s: writing 4CC command failed %d", __func__, ret);
+		return 1;
+	}
+
+	return 0;
+}
+
+#define TPS_POWER_STATUS_PWROPMODE(x)	    FIELD_GET(GENMASK(3, 2), x)
+
+#define TPS_PDO_CONTRACT_TYPE(x)	FIELD_GET(GENMASK(31, 30), x)
+#define TPS_PDO_CONTRACT_FIXED	0
+#define TPS_PDO_CONTRACT_BATTERY	1
+#define TPS_PDO_CONTRACT_VARIABLE	2
+
+#define TPS_TYPEC_PWR_MODE_USB	0
+#define TPS_TYPEC_PWR_MODE_1_5A	1
+#define TPS_TYPEC_PWR_MODE_3_0A	2
+#define TPS_TYPEC_PWR_MODE_PD	3
+
+#define TPS_PDO_FIXED_CONTRACT_MAX_CURRENT(x)	(FIELD_GET(GENMASK(9, 0), x) * 10)
+#define TPS_PDO_VAR_CONTRACT_MAX_CURRENT(x)	(FIELD_GET(GENMASK(9, 0), x) * 10)
+#define TPS_PDO_BAT_CONTRACT_MAX_VOLTAGE(x)	(FIELD_GET(GENMASK(29, 20), x) * 50)
+#define TPS_PDO_BAT_CONTRACT_MAX_POWER(x)	(FIELD_GET(GENMASK(9, 0), x) * 250)
+
+int tps65982_get_max_current(void)
+{
+	int ret;
+	u8 buf[7];
+	u8 pwr_status;
+	u32 contract;
+	int type, mode;
+	struct udevice *udev, *bus;
+
+	log_debug("%s: starting\n", __func__);
+
+	/* Set the i2c bus */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
+	if (ret) {
+		log_debug("%s: No bus %d\n", __func__, 0);
+		return -1;
+	}
+
+	ret = i2c_get_chip(bus, 0x3f, 1, &udev);
+	if (ret) {
+		log_debug("%s: setting chip offset failed %d\n", __func__, ret);
+		return -1;
+	}
+
+	ret = dm_i2c_read(udev, 0x3f, buf, 3);
+	if (ret) {
+		log_debug("%s: reading pwr_status failed %d\n", __func__, ret);
+		return -1;
+	}
+
+	pwr_status = buf[1];
+
+	if (!(pwr_status & 1))
+		return 0;
+
+	mode = TPS_POWER_STATUS_PWROPMODE(pwr_status);
+	switch (mode) {
+	case TPS_TYPEC_PWR_MODE_1_5A:
+		return 1500;
+	case TPS_TYPEC_PWR_MODE_3_0A:
+		return 3000;
+	case TPS_TYPEC_PWR_MODE_PD:
+		ret = dm_i2c_read(udev, 0x34, buf, 7);
+		if (ret) {
+			log_debug("%s: reading active contract failed %d\n", __func__, ret);
+			return -1;
+		}
+
+		contract = buf[1] + (buf[2] << 8) + (buf[3] << 16) + (buf[4] << 24);
+
+		type = TPS_PDO_CONTRACT_TYPE(contract);
+
+		switch (type) {
+		case TPS_PDO_CONTRACT_FIXED:
+			return TPS_PDO_FIXED_CONTRACT_MAX_CURRENT(contract);
+		case TPS_PDO_CONTRACT_BATTERY:
+			return 1000 * TPS_PDO_BAT_CONTRACT_MAX_POWER(contract)
+				/ TPS_PDO_BAT_CONTRACT_MAX_VOLTAGE(contract);
+		case TPS_PDO_CONTRACT_VARIABLE:
+			return TPS_PDO_VAR_CONTRACT_MAX_CURRENT(contract);
+		default:
+			log_debug("Unknown contract type: %d\n", type);
+			return -1;
+		}
+	case TPS_TYPEC_PWR_MODE_USB:
+		return 500;
+	default:
+		log_debug("Unknown power mode: %d\n", mode);
+		return -1;
+	}
+}
+
+int init_tps65982(void)
+{
+	log_debug("%s: starting\n", __func__);
+
+	if (tps65982_wait_for_app(500, 100)) {
+		log_err("tps65982 APP boot failed\n");
+		return 1;
+	}
+
+	log_info("tps65982 boot successful\n");
+	return 0;
+}
+
+int bq25895_set_iinlim(int current)
+{
+	u8 val, iinlim;
+	int ret;
+	struct udevice *udev, *bus;
+
+	/* Set the i2c bus */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 3, &bus);
+	if (ret) {
+		log_err("%s: No bus 3\n", __func__);
+		return ret;
+	}
+
+	ret = i2c_get_chip(bus, 0x6a, 1, &udev);
+	if (ret) {
+		log_err("%s: setting chip offset failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	if (current > 3250)
+		current = 3250;
+	if (current < 100)
+		current = 100;
+
+	val = dm_i2c_reg_read(udev, 0x00);
+	iinlim = ((current - 100) / 50) & 0x3f;
+	val = (val & 0xc0) | iinlim;
+	dm_i2c_reg_write(udev, 0x00, val);
+	log_debug("REG00 0x%x\n", val);
+
+	return 0;
+}
+
+bool bq25895_battery_present(void)
+{
+	u8 val;
+	int ret;
+	struct udevice *udev, *bus;
+
+	/* Set the i2c bus */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 3, &bus);
+	if (ret) {
+		log_err("%s: No bus 3\n", __func__);
+		return ret;
+	}
+
+	ret = i2c_get_chip(bus, 0x6a, 1, &udev);
+	if (ret) {
+		log_err("%s: setting chip offset failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* note that this may return false negatives when there's
+	 * no external power applied and the battery voltage is below
+	 * Vsys. this isn't a problem when used for clearing the dead
+	 * battery flag though, since it's certain that there's an external
+	 * power applied in this case
+	 */
+	val = dm_i2c_reg_read(udev, 0x0e) & 0x7f;
+	if (val == 0x00 || val == 0x7f)
+		return false;
+
+	return true;
+}
+
+/*
+ * set some safe defaults for the battery charger
+ */
+int init_charger_bq25895(void)
+{
+	u8 val;
+	int iinlim, ret;
+	struct udevice *udev, *bus;
+
+	/* Set the i2c bus */
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 3, &bus);
+	if (ret) {
+		log_debug("%s: No bus 3\n", __func__);
+		return ret;
+	}
+
+	ret = i2c_get_chip(bus, 0x6a, 1, &udev);
+	if (ret) {
+		log_debug("%s: setting chip offset failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	val = dm_i2c_reg_read(udev, 0x0b);
+	log_debug("REG0B 0x%x\n", val);
+
+	log_debug("VBUS_STAT 0x%x\n", val >> 5);
+	switch (val >> 5) {
+	case 0:
+		log_debug("VBUS not detected\n");
+		break;
+	case 1:
+		log_debug("USB SDP IINLIM 500mA\n");
+		break;
+	case 2:
+		log_debug("USB CDP IINLIM 1500mA\n");
+		break;
+	case 3:
+		log_debug("USB DCP IINLIM 3500mA\n");
+		break;
+	case 4:
+		log_debug("MAXCHARGE IINLIM 1500mA\n");
+		break;
+	case 5:
+		log_debug("Unknown IINLIM 500mA\n");
+		break;
+	case 6:
+		log_debug("DIVIDER IINLIM > 1000mA\n");
+		break;
+	case 7:
+		log_debug("OTG\n");
+		break;
+	};
+
+	log_debug("CHRG_STAT 0x%x\n", (val >> 3) & 0x3);
+	log_debug("PG_STAT 0x%x\n", (val >> 2) & 1);
+	log_debug("SDP_STAT 0x%x\n", (val >> 1) & 1);
+	log_debug("VSYS_STAT 0x%x\n", val & 1);
+
+	val = dm_i2c_reg_read(udev, 0x00);
+	log_debug("REG00 0x%x\n", val);
+	iinlim = 100 + (val & 0x3f) * 50;
+	log_debug("IINLIM %d mA\n", iinlim);
+	log_debug("EN_HIZ 0x%x\n", (val >> 7) & 1);
+	log_debug("EN_ILIM 0x%x\n", (val >> 6) & 1);
+
+	/* set 1.6A charge limit */
+	dm_i2c_reg_write(udev, 0x04, 0x19);
+
+	/* re-enable charger */
+	val = dm_i2c_reg_read(udev, 0x03);
+	val = val | 0x10;
+	dm_i2c_reg_write(udev, 0x03, val);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct udevice *dev;
+	int tps_ret;
+
+	if (IS_ENABLED(CONFIG_USB_DWC3) || IS_ENABLED(CONFIG_USB_XHCI_IMX8M)) {
+		log_debug("%s: initializing USB clk\n", __func__);
+
+		/* init_usb_clk won't enable the second clock if it's a USB boot */
+		if (is_usb_boot()) {
+			clock_enable(CCGR_USB_CTRL2, 1);
+			clock_enable(CCGR_USB_PHY2, 1);
+		}
+
+		printf("Enabling regulator-hub\n");
+		if (!regulator_get_by_devname("regulator-hub", &dev)) {
+			if (regulator_set_enable(dev, true))
+				pr_err("Failed to enable regulator-hub\n");
+		}
+	}
+
+	tps_ret = init_tps65982();
+	init_charger_bq25895();
+
+	if (!tps_ret) {
+		int current = tps65982_get_max_current();
+
+		if (current > 500)
+			bq25895_set_iinlim(current);
+
+		if (bq25895_battery_present())
+			tps65982_clear_dead_battery();
+	}
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+		u32 rev;
+		char rev_str[3];
+
+		env_set("board_name", "librem5");
+		if (fuse_read(9, 0, &rev)) {
+			env_set("board_rev", BOARD_REV_ERROR);
+		} else if (rev == 0) {
+			env_set("board_rev", BOARD_REV_UNKNOWN);
+		} else if (rev > 0) {
+			sprintf(rev_str, "%u", rev);
+			env_set("board_rev", rev_str);
+		}
+
+		printf("Board name: %s\n", env_get("board_name"));
+		printf("Board rev:  %s\n", env_get("board_rev"));
+	}
+
+	if (is_usb_boot()) {
+		puts("USB Boot\n");
+		env_set("bootcmd", "fastboot 0");
+	}
+
+	return 0;
+}
diff --git a/board/purism/librem5/librem5.h b/board/purism/librem5/librem5.h
new file mode 100644
index 00000000000..0d24edea9b1
--- /dev/null
+++ b/board/purism/librem5/librem5.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Purism
+ */
+
+#ifndef __LIBREM5_H__
+#define __LIBREM5_H__
+
+#define CAMERA_EN IMX_GPIO_NR(1, 0)
+#define SD_EN IMX_GPIO_NR(1, 3)
+#define AUDIO_EN IMX_GPIO_NR(1, 4)
+#define DSI_EN IMX_GPIO_NR(1, 5)
+#define SMC_EN IMX_GPIO_NR(1, 6)
+#define TYPEC_MUX_EN IMX_GPIO_NR(1, 11)
+#define HUB_NRESET IMX_GPIO_NR(1, 12)
+#define HUB_EN IMX_GPIO_NR(1, 14)
+#define VOL_UP IMX_GPIO_NR(1, 16)
+#define VOL_DOWN IMX_GPIO_NR(1, 17)
+#define DSI_BIAS_EN IMX_GPIO_NR(1, 20)
+#define FLASH_EN IMX_GPIO_NR(1, 23)
+#define WWAN_NRESET IMX_GPIO_NR(3, 1)
+#define CHG_EN IMX_GPIO_NR(3, 2)
+#define CHG_OTG_OUT_EN IMX_GPIO_NR(3, 4)
+#define WIFI_EN IMX_GPIO_NR(3, 10)
+#define GPS_EN IMX_GPIO_NR(3, 12)
+#define BL_EN IMX_GPIO_NR(3, 14)
+#define WWAN_EN IMX_GPIO_NR(3, 18)
+#define NFC_EN IMX_GPIO_NR(4, 28)
+#define LED_G IMX_GPIO_NR(5, 2)
+#define LED_R IMX_GPIO_NR(5, 3)
+#define LED_B IMX_GPIO_NR(1, 13)
+#define MOTO IMX_GPIO_NR(5, 5)
+#define SPI1_SCLK IMX_GPIO_NR(5, 6)
+#define SPI1_MOSI IMX_GPIO_NR(5, 7)
+#define SPI1_MISO IMX_GPIO_NR(5, 8)
+#define SPI1_SS0 IMX_GPIO_NR(5, 9)
+
+#define UART1_TX IMX_GPIO_NR(5, 23)
+#define UART1_RX IMX_GPIO_NR(5, 22)
+#define UART2_TX IMX_GPIO_NR(5, 25)
+#define UART2_RX IMX_GPIO_NR(5, 24)
+#define UART3_TX IMX_GPIO_NR(5, 27)
+#define UART3_RX IMX_GPIO_NR(5, 26)
+#define UART4_TX IMX_GPIO_NR(5, 11)
+#define UART4_RX IMX_GPIO_NR(5, 10)
+
+#define TPS_RESET IMX_GPIO_NR(3, 24)
+
+#define PURISM_VID	0x316d
+#define PURISM_PID	0x4c05
+
+#define BOARD_REV_ERROR		"unknown"
+#define BOARD_REV_BIRCH		"1"
+#define BOARD_REV_CHESTNUT	"2"
+#define BOARD_REV_DOGWOOD	"3"
+#define BOARD_REV_EVERGREEN	"4"
+/* Could be ASPEN, BIRCH or CHESTNUT. assume CHESTNUT */
+#define BOARD_REV_UNKNOWN	BOARD_REV_CHESTNUT
+
+#ifdef CONFIG_SPL_BUILD
+static const iomux_v3_cfg_t configure_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_ENET_MDC__GPIO1_IO16 | MUX_PAD_CTRL(PAD_CTL_PUE),
+	IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17 | MUX_PAD_CTRL(PAD_CTL_PUE),
+	IMX8MQ_PAD_ENET_TD1__GPIO1_IO20 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_TXC__GPIO1_IO23 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_DQS__GPIO3_IO14 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+	IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
+};
+
+static inline void init_pinmux(void)
+{
+	imx_iomux_v3_setup_multiple_pads(configure_pads, ARRAY_SIZE(configure_pads));
+
+	gpio_request(LED_R, "LED_R");
+	gpio_request(LED_G, "LED_G");
+	gpio_request(LED_B, "LED_B");
+	gpio_request(VOL_UP, "VOL_UP");
+	gpio_request(VOL_DOWN, "VOL_DOWN");
+
+	gpio_request(NFC_EN, "NFC_EN");
+	gpio_request(CHG_EN, "CHG_EN");
+	gpio_request(CHG_OTG_OUT_EN, "CHG_OTG_OUT_EN");
+
+	gpio_request(TYPEC_MUX_EN, "TYPEC_MUX_EN");
+
+	gpio_request(TPS_RESET, "TPS_RESET");
+
+	gpio_request(WWAN_EN, "WWAN_EN");
+	gpio_request(WWAN_NRESET, "WWAN_NRESET");
+
+	gpio_request(HUB_EN, "HUB_EN");
+	gpio_request(HUB_NRESET, "HUB_NRESET");
+	gpio_request(SD_EN, "SD_EN");
+	gpio_request(AUDIO_EN, "AUDIO_EN");
+	gpio_request(DSI_EN, "DSI_EN");
+	gpio_request(SMC_EN, "SMC_EN");
+	gpio_request(CAMERA_EN, "CAMERA_EN");
+	gpio_request(FLASH_EN, "FLASH_EN");
+	gpio_request(DSI_BIAS_EN, "DSI_BIAS_EN");
+	gpio_request(GPS_EN, "GPS_EN");
+	gpio_request(BL_EN, "BL_EN");
+#ifndef CONSOLE_ON_UART4
+	gpio_request(WIFI_EN, "WIFI_EN");
+	gpio_direction_output(WIFI_EN, 0);
+#endif /* CONSOLE_ON_UART4 */
+	gpio_direction_input(VOL_UP);
+	gpio_direction_input(VOL_DOWN);
+
+	/* ensure charger is in the automated mode */
+	gpio_direction_output(NFC_EN, 0);
+	gpio_direction_output(CHG_EN, 0);
+	gpio_direction_output(CHG_OTG_OUT_EN, 0);
+
+	gpio_direction_input(TYPEC_MUX_EN);
+
+	gpio_direction_output(TPS_RESET, 0);
+
+	gpio_direction_output(WWAN_EN, 0);
+	gpio_direction_output(WWAN_NRESET, 1);
+
+	gpio_direction_output(HUB_EN, 1);
+	gpio_direction_output(HUB_NRESET, 1);
+	mdelay(10);
+	gpio_direction_output(SD_EN, 1);
+	gpio_direction_output(SMC_EN, 0);
+	gpio_direction_output(CAMERA_EN, 0);
+	gpio_direction_output(FLASH_EN, 0);
+	gpio_direction_output(DSI_BIAS_EN, 0);
+	gpio_direction_output(GPS_EN, 0);
+	gpio_direction_output(BL_EN, 0);
+
+	/* turn these on for i2c busses */
+	gpio_direction_output(AUDIO_EN, 1);
+	gpio_direction_output(DSI_EN, 1);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+#define USB1_BASE_ADDR         0x38100000
+#define USB2_BASE_ADDR         0x38200000
+#define USB1_PHY_BASE_ADDR     0x381F0000
+#define USB2_PHY_BASE_ADDR     0x382F0000
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+#define USB_PHY_CTRL0_SSC_RANGE_MASK	GENMASK(23, 21)
+#define USB_PHY_CTRL0_SSC_RANGE_4003PPM	(0x2 << 21)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+#define USB_PHY_CTRL6			0x18
+#define USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL	BIT(29)
+
+extern struct dram_timing_info dram_timing_b0;
+
+#endif
diff --git a/board/purism/librem5/lpddr4_timing.c b/board/purism/librem5/lpddr4_timing.c
new file mode 100644
index 00000000000..46bc7f8591c
--- /dev/null
+++ b/board/purism/librem5/lpddr4_timing.c
@@ -0,0 +1,1324 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+#define WR_POST_EXT_3200	/* recommened to define */
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0), 0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0), 0xa3080020 },
+	{ DDRC_MSTR2(0), 0x00000000 },
+	{ DDRC_RFSHTMG(0), 0x006100E0 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+#ifdef WR_POST_EXT_3200
+	{ DDRC_INIT4(0), 0x00330008 },
+#else
+	{ DDRC_INIT4(0), 0x00310008 },
+#endif
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+
+	{ DDRC_DBICTL(0), 0x00000001 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x00000015 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001F1F },
+	/* bank interleave */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0x08080707 },
+
+	/* performance setting */
+	{ DDRC_ODTCFG(0), 0x0b060908 },
+	{ DDRC_ODTMAP(0), 0x00000000 },
+	{ DDRC_SCHED(0), 0x29511505 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x00000016 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00000011 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGR_0(0), 0x000010f3 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+
+	/* Frequency 1: 400mbps */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+	/* Frequency 2: 100mbps */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x20110, 0x02 },
+	{ 0x20111, 0x03 },
+	{ 0x20112, 0x04 },
+	{ 0x20113, 0x05 },
+	{ 0x20114, 0x00 },
+	{ 0x20115, 0x01 },
+
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+#ifdef WR_POST_EXT_3200
+	{ 0x20024, 0xeb },
+#else
+	{ 0x20024, 0xab },
+#endif
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0xab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0xab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+	{ 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x2200c7, 0x80 },
+	{ 0x200ca, 0x106 },
+	{ 0x1200ca, 0x106 },
+	{ 0x2200ca, 0x106 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+
+	{ 0x54019, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	/* MR3/MR2 */
+#ifdef WR_POST_EXT_3200
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
+#else
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
+#endif
+	/* MR11/MR4 */
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	/* self:0x284d//MR13/MR12 */
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
+	/* MR16/MR14*/
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
+	/* MR1 */
+	{ 0x54038, 0xd400 },
+	/* MR3/MR2 */
+#ifdef WR_POST_EXT_3200
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
+#else
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
+#endif
+	/* MR11/MR4 */
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	/* self:0x284d//MR13/MR12 */
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
+	/* MR16/MR14 */
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
+	/* { 0x5403d, 0x500 } */
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	/* PHY Ron/Rtt */
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, LPDDR4_TRAIN_SEQ_400 },
+	{ 0x54009, LPDDR4_HDT_CTL_400_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	/* MR4/MR3 */
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
+	/* MR12/MR11 */
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ)/*0x4d46*/ },
+	/* self:0x4d28//MR14/MR13 */
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
+	/* self:0x4d28//MR14/MR13 */
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, LPDDR4_TRAIN_SEQ_100 },
+	{ 0x54009, LPDDR4_HDT_CTL_100_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
+		    LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
+	{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_2D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
+	{ 0x54010, LPDDR4_2D_WEIGHT },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+#else
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+#endif
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+
+	{ 0x54032, 0xd400 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+#else
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
+#endif
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0xd400 },
+#ifdef WR_POST_EXT_3200
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+#else
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
+#endif
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/board/purism/librem5/lpddr4_timing_b0.c b/board/purism/librem5/lpddr4_timing_b0.c
new file mode 100644
index 00000000000..ec68edaf690
--- /dev/null
+++ b/board/purism/librem5/lpddr4_timing_b0.c
@@ -0,0 +1,1191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+#define WR_POST_EXT_3200  /* recommened to define */
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
+	{ DDRC_DBG1(0), 0x00000001 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0), 0xa3080020 },
+	{ DDRC_MSTR2(0), 0x00000000 },
+	{ DDRC_RFSHTMG(0), 0x006100E0 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+#ifdef WR_POST_EXT_3200  /* recommened to define */
+	{ DDRC_INIT4(0), 0x00330008 },
+#else
+	{ DDRC_INIT4(0), 0x00310008 },
+#endif
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+
+	{ DDRC_DBICTL(0), 0x00000001 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
+
+	/* need be refined by ddrphy trained value */
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+
+	/* address mapping */
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+	{ DDRC_ADDRMAP0(0), 0x00000015 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	/* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x00001F1F },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), 0x08080707 },
+
+	/* 667mts frequency setting */
+	{ DDRC_FREQ1_DERATEEN(0), 0x0000000 },
+	{ DDRC_FREQ1_DERATEINT(0), 0x0800000 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x014001E },
+	{ DDRC_FREQ1_INIT3(0), 0x0140009 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x3858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x0000404 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0000502 },
+
+	/* performance setting */
+	{ DDRC_ODTCFG(0), 0x0b060908 },
+	{ DDRC_ODTMAP(0), 0x00000000 },
+	{ DDRC_SCHED(0), 0x29511505 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x00000016 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00000011 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGR_0(0), 0x000010f3 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+	{ DDRC_FREQ1_DERATEEN(0), 0x00000202 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x20110, 0x02 }, /* MapCAB0toDFI */
+	{ 0x20111, 0x03 }, /* MapCAB1toDFI */
+	{ 0x20112, 0x04 }, /* MapCAB2toDFI */
+	{ 0x20113, 0x05 }, /* MapCAB3toDFI */
+	{ 0x20114, 0x00 }, /* MapCAB4toDFI */
+	{ 0x20115, 0x01 }, /* MapCAB5toDFI */
+
+	/* Initialize PHY Configuration */
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+	{ 0x20024, 0xe3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0xa3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0xa3 },
+	{ 0x2003a, 0x2 },
+
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0xa7 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x600 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5655 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x29c },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x914 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401e, 0x6 },
+	{ 0x5401f, 0x914 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x1400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, 0x600 },
+	{ 0x54038, 0x1400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0xd0000, 0x1 },
+
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_2D },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
+	{ 0x54010, LPDDR4_2D_WEIGHT },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x310 },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54024, 0x5 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
+		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1 },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0xd },
+	{ 0x900a5, 0x7c0 },
+	{ 0x900a6, 0x109 },
+	{ 0x900a7, 0x4 },
+	{ 0x900a8, 0x7c0 },
+	{ 0x900a9, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900aa, 0x0 },
+	{ 0x900ab, 0x790 },
+	{ 0x900ac, 0x11a },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x7aa },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x7b2 },
+	{ 0x900b2, 0x2a },
+	{ 0x900b3, 0x0 },
+	{ 0x900b4, 0x7c8 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x10 },
+	{ 0x900b7, 0x10 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x10 },
+	{ 0x900ba, 0x2a8 },
+	{ 0x900bb, 0x129 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x370 },
+	{ 0x900be, 0x129 },
+	{ 0x900bf, 0xa },
+	{ 0x900c0, 0x3c8 },
+	{ 0x900c1, 0x1a9 },
+	{ 0x900c2, 0xc },
+	{ 0x900c3, 0x408 },
+	{ 0x900c4, 0x199 },
+	{ 0x900c5, 0x14 },
+	{ 0x900c6, 0x790 },
+	{ 0x900c7, 0x11a },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x18 },
+	{ 0x900cb, 0xe },
+	{ 0x900cc, 0x408 },
+	{ 0x900cd, 0x199 },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x8568 },
+	{ 0x900d0, 0x108 },
+	{ 0x900d1, 0x18 },
+	{ 0x900d2, 0x790 },
+	{ 0x900d3, 0x16a },
+	{ 0x900d4, 0x8 },
+	{ 0x900d5, 0x1d8 },
+	{ 0x900d6, 0x169 },
+	{ 0x900d7, 0x10 },
+	{ 0x900d8, 0x8558 },
+	{ 0x900d9, 0x168 },
+	{ 0x900da, 0x70 },
+	{ 0x900db, 0x788 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x1ff8 },
+	{ 0x900de, 0x85a8 },
+	{ 0x900df, 0x1e8 },
+	{ 0x900e0, 0x50 },
+	{ 0x900e1, 0x798 },
+	{ 0x900e2, 0x16a },
+	{ 0x900e3, 0x60 },
+	{ 0x900e4, 0x7a0 },
+	{ 0x900e5, 0x16a },
+	{ 0x900e6, 0x8 },
+	{ 0x900e7, 0x8310 },
+	{ 0x900e8, 0x168 },
+	{ 0x900e9, 0x8 },
+	{ 0x900ea, 0xa310 },
+	{ 0x900eb, 0x168 },
+	{ 0x900ec, 0xa },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x6e },
+	{ 0x900f0, 0x0 },
+	{ 0x900f1, 0x68 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0x408 },
+	{ 0x900f4, 0x169 },
+	{ 0x900f5, 0x0 },
+	{ 0x900f6, 0x8310 },
+	{ 0x900f7, 0x168 },
+	{ 0x900f8, 0x0 },
+	{ 0x900f9, 0xa310 },
+	{ 0x900fa, 0x168 },
+	{ 0x900fb, 0x1ff8 },
+	{ 0x900fc, 0x85a8 },
+	{ 0x900fd, 0x1e8 },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x798 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x78 },
+	{ 0x90102, 0x7a0 },
+	{ 0x90103, 0x16a },
+	{ 0x90104, 0x68 },
+	{ 0x90105, 0x790 },
+	{ 0x90106, 0x16a },
+	{ 0x90107, 0x8 },
+	{ 0x90108, 0x8b10 },
+	{ 0x90109, 0x168 },
+	{ 0x9010a, 0x8 },
+	{ 0x9010b, 0xab10 },
+	{ 0x9010c, 0x168 },
+	{ 0x9010d, 0xa },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x58 },
+	{ 0x90111, 0x0 },
+	{ 0x90112, 0x68 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0x408 },
+	{ 0x90115, 0x169 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x8b10 },
+	{ 0x90118, 0x168 },
+	{ 0x90119, 0x0 },
+	{ 0x9011a, 0xab10 },
+	{ 0x9011b, 0x168 },
+	{ 0x9011c, 0x0 },
+	{ 0x9011d, 0x1d8 },
+	{ 0x9011e, 0x169 },
+	{ 0x9011f, 0x80 },
+	{ 0x90120, 0x790 },
+	{ 0x90121, 0x16a },
+	{ 0x90122, 0x18 },
+	{ 0x90123, 0x7aa },
+	{ 0x90124, 0x6a },
+	{ 0x90125, 0xa },
+	{ 0x90126, 0x0 },
+	{ 0x90127, 0x1e9 },
+	{ 0x90128, 0x8 },
+	{ 0x90129, 0x8080 },
+	{ 0x9012a, 0x108 },
+	{ 0x9012b, 0xf },
+	{ 0x9012c, 0x408 },
+	{ 0x9012d, 0x169 },
+	{ 0x9012e, 0xc },
+	{ 0x9012f, 0x0 },
+	{ 0x90130, 0x68 },
+	{ 0x90131, 0x9 },
+	{ 0x90132, 0x0 },
+	{ 0x90133, 0x1a9 },
+	{ 0x90134, 0x0 },
+	{ 0x90135, 0x408 },
+	{ 0x90136, 0x169 },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8080 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0x8 },
+	{ 0x9013b, 0x7aa },
+	{ 0x9013c, 0x6a },
+	{ 0x9013d, 0x0 },
+	{ 0x9013e, 0x8568 },
+	{ 0x9013f, 0x108 },
+	{ 0x90140, 0xb7 },
+	{ 0x90141, 0x790 },
+	{ 0x90142, 0x16a },
+	{ 0x90143, 0x1f },
+	{ 0x90144, 0x0 },
+	{ 0x90145, 0x68 },
+	{ 0x90146, 0x8 },
+	{ 0x90147, 0x8558 },
+	{ 0x90148, 0x168 },
+	{ 0x90149, 0xf },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0xc },
+	{ 0x9014d, 0x0 },
+	{ 0x9014e, 0x68 },
+	{ 0x9014f, 0x0 },
+	{ 0x90150, 0x408 },
+	{ 0x90151, 0x169 },
+	{ 0x90152, 0x0 },
+	{ 0x90153, 0x8558 },
+	{ 0x90154, 0x168 },
+	{ 0x90155, 0x8 },
+	{ 0x90156, 0x3c8 },
+	{ 0x90157, 0x1a9 },
+	{ 0x90158, 0x3 },
+	{ 0x90159, 0x370 },
+	{ 0x9015a, 0x129 },
+	{ 0x9015b, 0x20 },
+	{ 0x9015c, 0x2aa },
+	{ 0x9015d, 0x9 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x400 },
+	{ 0x90160, 0x10e },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0xe8 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0x0 },
+	{ 0x90165, 0x8140 },
+	{ 0x90166, 0x10c },
+	{ 0x90167, 0x10 },
+	{ 0x90168, 0x8138 },
+	{ 0x90169, 0x10c },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x7c8 },
+	{ 0x9016c, 0x101 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x0 },
+	{ 0x9016f, 0x8 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0x448 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0xf },
+	{ 0x90174, 0x7c0 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x0 },
+	{ 0x90177, 0xe8 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x47 },
+	{ 0x9017a, 0x630 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x618 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0xe0 },
+	{ 0x90181, 0x109 },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x7c8 },
+	{ 0x90184, 0x109 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x8140 },
+	{ 0x90187, 0x10c },
+	{ 0x90188, 0x0 },
+	{ 0x90189, 0x1 },
+	{ 0x9018a, 0x8 },
+	{ 0x9018b, 0x8 },
+	{ 0x9018c, 0x4 },
+	{ 0x9018d, 0x8 },
+	{ 0x9018e, 0x8 },
+	{ 0x9018f, 0x7c8 },
+	{ 0x90190, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2b },
+	{ 0x90026, 0x6c },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x1a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing_b0 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	/*
+	 * this table must be initialized if DDRPHY bypass mode is
+	 * not used: all fsp drate > 666MTS.
+	 */
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c
new file mode 100644
index 00000000000..a068f76460d
--- /dev/null
+++ b/board/purism/librem5/spl.c
@@ -0,0 +1,592 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2021 Purism
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <hang.h>
+#include <init.h>
+#include <spl.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <linux/delay.h>
+#include "librem5.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+	if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
+		ddr_init(&dram_timing);
+	else
+		ddr_init(&dram_timing_b0);
+}
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	log_debug("%s : starting\n", __func__);
+
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+#define ECSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+static const iomux_v3_cfg_t ecspi_pads[] = {
+	IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
+	IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
+	IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
+	IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL),
+};
+
+int board_ecspi_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi_pads, ARRAY_SIZE(ecspi_pads));
+
+	return 0;
+}
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+	return (bus == 0 && cs == 0) ? (SPI1_SS0) : -1;
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_ODE | PAD_CTL_DSE7 | PAD_CTL_FSEL3)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | PC,
+		.gp = IMX_GPIO_NR(5, 16),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | PC,
+		.gp = IMX_GPIO_NR(5, 17),
+	},
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | PC,
+		.gp = IMX_GPIO_NR(5, 18),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | PC,
+		.gp = IMX_GPIO_NR(5, 19),
+	},
+};
+
+struct i2c_pads_info i2c_pad_info4 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | PC,
+		.gp = IMX_GPIO_NR(5, 20),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | PC,
+		.gp = IMX_GPIO_NR(5, 21),
+	},
+};
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+	}
+
+	return ret;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL1)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static const iomux_v3_cfg_t usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		log_debug("Initializing FSL USDHC port %d\n", i);
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			log_err("Warning: USDHC controller(%d) not supported\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define LDO_VOLT_EN                     BIT(6)
+
+/*
+ * Disable the charger - it will be re-enabled in u-boot
+ */
+void disable_charger_bq25895(void)
+{
+	u8 val;
+	int timeout = 1000; // ms
+
+	/* Set the i2c bus */
+	i2c_set_bus_num(3);
+
+	/* disable ship mode if BATFET_DLY is set */
+	val = i2c_reg_read(0x6a, 0x09);
+	log_debug("REG09 0x%x\n", val);
+	if (val & 0x28) {
+		val = val & ~0x28;
+		i2c_reg_write(0x6a, 0x09, val);
+	}
+
+	/* disable and trigger DPDM, ICO, HVDCP and MaxCharge */
+	val = i2c_reg_read(0x6a, 0x02);
+	log_debug("REG02 0x%x\n", val);
+	val &= 0xe0;
+	i2c_reg_write(0x6a, 0x02, val);
+
+	/* disable charger and enable BAT_LOADEN */
+	val = i2c_reg_read(0x6a, 0x03);
+	log_debug("REG03 0x%x\n", val);
+	val = (val | 0x80) & ~0x10;
+	i2c_reg_write(0x6a, 0x03, val);
+
+	mdelay(10);
+
+	/* force ADC conversions */
+	val = i2c_reg_read(0x6a, 0x02);
+	log_debug("REG02 0x%x\n", val);
+	val = (val | 0x80) & ~0x40;
+	i2c_reg_write(0x6a, 0x02, val);
+
+	do {
+		mdelay(10);
+		timeout -= 10;
+	} while ((i2c_reg_read(0x6a, 0x02) & 0x80) && (timeout > 0));
+
+	/* enable STAT pin */
+	val = i2c_reg_read(0x6a, 0x07);
+	log_debug("REG07 0x%x\n", val);
+	val = val & ~0x40;
+	i2c_reg_write(0x6a, 0x07, val);
+
+	/* check VBUS */
+	val = i2c_reg_read(0x6a, 0x11);
+	log_debug("VBUS good %d\n", (val >> 7) & 1);
+	log_debug("VBUS mV %d\n", (val & 0x7f) * 100 + 2600);
+
+	/* check VBAT */
+	val = i2c_reg_read(0x6a, 0x0e);
+	log_debug("VBAT mV %d\n", (val & 0x7f) * 20 + 2304);
+
+	/* limit the VINDPM to 3.9V  */
+	i2c_reg_write(0x6a, 0x0d, 0x8d);
+
+	/* set the max voltage to 4.192V */
+	val = i2c_reg_read(0x6a, 0x6);
+	val = (val & ~0xFC) | 0x16 << 2;
+	i2c_reg_write(0x6a, 0x6, val);
+
+	/* set the SYS_MIN to 3.7V */
+	val = i2c_reg_read(0x6a, 0x3);
+	val = val | 0xE;
+	i2c_reg_write(0x6a, 0x3, val);
+
+	/* disable BAT_LOADEN */
+	val = i2c_reg_read(0x6a, 0x03);
+	log_debug("REG03 0x%x\n", val);
+	val = val & ~0x80;
+	i2c_reg_write(0x6a, 0x03, val);
+}
+
+#define I2C_PMIC	0
+
+int power_bd71837_init(unsigned char bus)
+{
+	static const char name[] = BD718XX_REGULATOR_DRIVER;
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		log_err("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = name;
+	p->interface = I2C_PMIC;
+	p->number_of_regs = BD718XX_MAX_REGISTER;
+	p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ldo[] = {BD718XX_LDO5_VOLT, BD718XX_LDO6_VOLT,
+		     BD71837_LDO7_VOLT};
+	u32 val;
+	int i, rv;
+
+	/* Set the i2c bus */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	/*
+	 * Init PMIC
+	 */
+	rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS);
+	if (rv) {
+		log_err("%s: power_bd71837_init(%d) error %d\n", __func__,
+			CONFIG_POWER_BD71837_I2C_BUS, rv);
+		goto out;
+	}
+
+	p = pmic_get(BD718XX_REGULATOR_DRIVER);
+	if (!p) {
+		log_err("%s: pmic_get(%s) failed\n", __func__, BD718XX_REGULATOR_DRIVER);
+		rv = -ENODEV;
+		goto out;
+	}
+
+	rv = pmic_probe(p);
+	if (rv) {
+		log_err("%s: pmic_probe() error %d\n", __func__, rv);
+		goto out;
+	}
+
+	/*
+	 * Unlock all regs
+	 */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0);
+
+	/* find the reset cause */
+	pmic_reg_read(p, 0x29, &val);
+	log_debug("%s: reset cause %d\n", __func__, val);
+
+	/*
+	 * Reconfigure default voltages and disable:
+	 * - BUCK3: VDD_GPU_0V9 (1.00 -> 0.90)
+	 * - BUCK4: VDD_VPU_0V9 (1.00 -> 0.90)
+	 */
+	pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
+	pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
+
+	/*
+	 * Enable PHYs voltages: LDO5-7
+	 */
+	for (i = 0; i < ARRAY_SIZE(ldo); i++) {
+		rv = pmic_reg_read(p, ldo[i], &val);
+		if (rv) {
+			log_err("%s: pmic_read(%x) error %d\n", __func__,
+				ldo[i], rv);
+			continue;
+		}
+
+		pmic_reg_write(p, ldo[i], val | LDO_VOLT_EN);
+	}
+
+	udelay(500);
+
+	rv = 0;
+out:
+	return rv;
+}
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	RegData &= ~USB_PHY_CTRL0_SSC_RANGE_MASK;
+	RegData |= USB_PHY_CTRL0_SSC_RANGE_4003PPM;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	/* Disable rx term override */
+	RegData = readl(dwc3->base + USB_PHY_CTRL6);
+	RegData &= ~USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
+	writel(RegData, dwc3->base + USB_PHY_CTRL6);
+}
+
+static struct dwc3_device dwc3_device0_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+static struct dwc3_device dwc3_device1_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = USB2_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_HOST,
+	.index = 1,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	printf("%s : index %d type %d\n", __func__, index, init);
+
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_nxp_usb_phy_init(&dwc3_device0_data);
+		ret = dwc3_uboot_init(&dwc3_device0_data);
+	}
+	if (index == 1 && init == USB_INIT_HOST) {
+		dwc3_nxp_usb_phy_init(&dwc3_device1_data);
+		ret = dwc3_uboot_init(&dwc3_device1_data);
+	}
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	u32 RegData;
+	struct dwc3_device *dwc3;
+
+	printf("%s : %d\n", __func__, index);
+
+	if (index == 0 && init == USB_INIT_DEVICE)
+		dwc3 = &dwc3_device0_data;
+	if (index == 1 && init == USB_INIT_HOST)
+		dwc3 = &dwc3_device1_data;
+
+	dwc3_uboot_exit(index);
+
+	/* reset the phy */
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	/* enable rx term override */
+	RegData = readl(dwc3->base + USB_PHY_CTRL6);
+	RegData |= USB_PHY_CTRL6_RXTERM_OVERRIDE_SEL;
+	writel(RegData, dwc3->base + USB_PHY_CTRL6);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	if (is_usb_boot())
+		puts("USB Boot\n");
+	else
+		puts("Normal Boot\n");
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	if (is_usb_boot())
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+	else
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	arch_cpu_init();
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	init_uart_clk(CONSOLE_UART_CLK);
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+#ifdef CONSOLE_ON_UART4
+	gpio_request(WIFI_EN, "WIFI_EN");
+	gpio_direction_output(WIFI_EN, 1);
+#endif
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		log_err("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	printf("Initializing pinmux\n");
+	init_pinmux();
+	gpio_direction_output(LED_G, 1);
+	gpio_direction_output(MOTO, 1);
+	mdelay(50);
+	gpio_direction_output(MOTO, 0);
+
+	/* Enable and configure i2c buses not used below */
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+
+	power_init_board();
+
+	disable_charger_bq25895();
+
+	/* initialize this for M4 even if u-boot doesn't have SF_CMD */
+	printf("Initializing ECSPI\n");
+	board_ecspi_init();
+
+	/* DDR initialization */
+	printf("Initializing DRAM\n");
+	spl_dram_init();
+}
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index 0352d341e75..daa1beb14f8 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <fdt_support.h>
 #include <init.h>
 #include <asm/global_data.h>
 #include <dm/uclass-internal.h>
@@ -19,9 +20,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* If the firmware passed a device tree use it for U-Boot DRAM setup. */
+/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */
 extern u64 rcar_atf_boot_args[];
 
+#define FDT_RPC_PATH	"/soc/spi@ee200000"
+
 int fdtdec_board_setup(const void *fdt_blob)
 {
 	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
@@ -81,7 +84,7 @@ static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
 	return 0;
 }
 
-int ft_board_setup(void *blob, struct bd_info *bd)
+static void scrub_duplicate_memory(void *blob)
 {
 	/*
 	 * Scrub duplicate /memory@* node entries here. Some R-Car DTs might
@@ -119,6 +122,45 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 		first_mem_node = 0;
 		mem = 0;
 	}
+}
+
+static void update_rpc_status(void *blob)
+{
+	void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+	int offset, enabled;
+
+	/*
+	 * Check if the DT fragment received from TF-A had its RPC-IF device node
+	 * enabled.
+	 */
+	if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+		return;
+
+	offset = fdt_path_offset(atf_fdt_blob, FDT_RPC_PATH);
+	if (offset < 0)
+		return;
+
+	enabled = fdtdec_get_is_enabled(atf_fdt_blob, offset);
+	if (!enabled)
+		return;
+
+	/*
+	 * Find the RPC-IF device node, and enable it if it has a flash subnode.
+	 */
+	offset = fdt_path_offset(blob, FDT_RPC_PATH);
+	if (offset < 0)
+		return;
+
+	if (fdt_subnode_offset(blob, offset, "flash") < 0)
+		return;
+
+	fdt_status_okay(blob, offset);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	scrub_duplicate_memory(blob);
+	update_rpc_status(blob);
 
 	return 0;
 }
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 6028a0b6de4..581a4df1cc4 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -494,7 +494,7 @@ static void sysconf_init(void)
 	ret = uclass_get_device_by_driver(UCLASS_PMIC,
 					  DM_DRIVER_GET(stm32mp_pwr_pmic),
 					  &pwr_dev);
-	if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) {
+	if (!ret) {
 		ret = uclass_get_device_by_driver(UCLASS_MISC,
 						  DM_DRIVER_GET(stm32mp_bsec),
 						  &dev);
@@ -555,9 +555,6 @@ static int board_stm32mp15x_dk2_init(void)
 	struct gpio_desc hdmi, audio;
 	int ret = 0;
 
-	if (!IS_ENABLED(CONFIG_DM_REGULATOR))
-		return -ENODEV;
-
 	/* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
 	node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
 	if (!ofnode_valid(node)) {
@@ -658,8 +655,7 @@ int board_init(void)
 	if (board_is_stm32mp15x_dk2())
 		board_stm32mp15x_dk2_init();
 
-	if (IS_ENABLED(CONFIG_DM_REGULATOR))
-		regulators_enable_boot_on(_DEBUG);
+	regulators_enable_boot_on(_DEBUG);
 
 	/*
 	 * sysconf initialisation done only when U-Boot is running in secure
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index ed34991377e..9fa7b7beb63 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -86,7 +86,6 @@ __weak void gpi2c_init(void)
 static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 					    u32 header, u32 size, uint8_t *ep)
 {
-	u32 hdr_read = 0xdeadbeef;
 	int rc;
 
 #if CONFIG_IS_ENABLED(DM_I2C)
@@ -113,10 +112,10 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 	 * We must allow for fall through to check the data if 2 byte
 	 * addressing works
 	 */
-	(void)dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
+	(void)dm_i2c_read(dev, 0, ep, size);
 
 	/* Corrupted data??? */
-	if (hdr_read != header) {
+	if (*((u32 *)ep) != header) {
 		/*
 		 * read the eeprom header using i2c again, but use only a
 		 * 2 byte address (some newer boards need this..)
@@ -125,16 +124,12 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 		if (rc)
 			return rc;
 
-		rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4);
+		rc = dm_i2c_read(dev, 0, ep, size);
 		if (rc)
 			return rc;
 	}
-	if (hdr_read != header)
+	if (*((u32 *)ep) != header)
 		return -1;
-
-	rc = dm_i2c_read(dev, 0, ep, size);
-	if (rc)
-		return rc;
 #else
 	u32 byte;
 
@@ -154,26 +149,21 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 	 * We must allow for fall through to check the data if 2 byte
 	 * addressing works
 	 */
-	(void)i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
+	(void)i2c_read(dev_addr, 0x0, byte, ep, size);
 
 	/* Corrupted data??? */
-	if (hdr_read != header) {
+	if (*((u32 *)ep) != header) {
 		/*
 		 * read the eeprom header using i2c again, but use only a
 		 * 2 byte address (some newer boards need this..)
 		 */
 		byte = 2;
-		rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
-			      4);
+		rc = i2c_read(dev_addr, 0x0, byte, ep, size);
 		if (rc)
 			return rc;
 	}
-	if (hdr_read != header)
+	if (*((u32 *)ep) != header)
 		return -1;
-
-	rc = i2c_read(dev_addr, 0x0, byte, ep, size);
-	if (rc)
-		return rc;
 #endif
 	return 0;
 }
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index 243c97e0ba0..fb9aae6c9c8 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -34,14 +34,11 @@ DECLARE_GLOBAL_DATA_PTR;
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	switch (boot_dev_spl) {
-	case MMC1_BOOT:
+	case MMC1_BOOT: /* eMMC */
 		return BOOT_DEVICE_MMC1;
-	case SD2_BOOT:
+	case SD2_BOOT: /* SD card */
 	case MMC2_BOOT:
 		return BOOT_DEVICE_MMC2;
-	case SD3_BOOT:
-	case MMC3_BOOT:
-		return BOOT_DEVICE_MMC1;
 	case USB_BOOT:
 		return BOOT_DEVICE_BOARD;
 	default:
@@ -56,6 +53,15 @@ void spl_dram_init(void)
 
 void spl_board_init(void)
 {
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize %s: %d\n", dev->name, ret);
+	}
+
 	/* Serial download mode */
 	if (is_usb_boot()) {
 		puts("Back to ROM, SDP\n");
@@ -74,7 +80,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-
 __weak void board_early_init(void)
 {
 	init_uart_clk(0);
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 7597cd81f94..bad8833b228 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -102,9 +102,6 @@ static void select_dt_from_module_version(void)
 	if (strcmp(variant, env_variant)) {
 		printf("Setting variant to %s\n", variant);
 		env_set("variant", variant);
-
-		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
-			env_save();
 	}
 }
 
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
index e3c1a1201da..783e2bd0d25 100644
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -108,9 +108,6 @@ static void select_dt_from_module_version(void)
 	if (strcmp(variant, env_variant)) {
 		printf("Setting variant to %s\n", variant);
 		env_set("variant", variant);
-
-		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
-			env_save();
 	}
 }