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authorGiulio Benetti2020-04-27 17:53:06 +0200
committerStefano Babic2020-05-01 19:03:25 +0200
commitea0f768e2c835d2b77bdc1db7d4ab1416e45e432 (patch)
tree3314f24e7ceaf59a0fdfa46e96a01892dcb5e77c /common/spl/spl_sdp.c
parent72fef43d4d4043cf62fc9d8da6b41fe17f3dfb5e (diff)
clk: imx: clk-imxrt1050: fix lcdif clock gate
LCDIF clock gate was wrong so set it according to RM. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'common/spl/spl_sdp.c')
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