diff options
| author | Bin Meng | 2018-06-03 19:04:17 -0700 |
|---|---|---|
| committer | Bin Meng | 2018-06-13 09:50:57 +0800 |
| commit | fb05f0b02b01aed48db48f02a15e52c6de2d0dac (patch) | |
| tree | d2c81587706d01d4ec701c6d34faf7c7e068ca8e /configs/cougarcanyon2_defconfig | |
| parent | 80abc8165e658f4538ef2ab00ceba118e097dbfd (diff) | |
x86: cougarcanyon2: Remove CONFIG_HAVE_INTEL_ME
As README.x86 already mentions, there are two SPI flashes mounted
on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively.
SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores
the actual BIOS image which is U-Boot. Building a single image with
both ME firmware and U-Boot does not make sense.
This also describes the exact flash location where the u-boot.rom
should be programmed in the documentation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/cougarcanyon2_defconfig')
| -rw-r--r-- | configs/cougarcanyon2_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 6c79b77d06c..04ad23262b8 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" CONFIG_TARGET_COUGARCANYON2=y +# CONFIG_HAVE_INTEL_ME is not set # CONFIG_ENABLE_MRC_CACHE is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" |