diff options
| author | Mario Six | 2019-01-21 09:18:03 +0100 |
|---|---|---|
| committer | Mario Six | 2019-05-21 07:52:33 +0200 |
| commit | fe7d654d04a4ba87813dcf8acb7a17373029770d (patch) | |
| tree | acff08e60a356274b602f42d44a975b7a279eca2 /configs/kmcoge5ne_defconfig | |
| parent | daac2086ce1a36ffbd603eb643f45d14faae40e7 (diff) | |
mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig
Migrate the BR/OR settings to Kconfig. These must be known at compile
time, so cannot be configured via DT.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'configs/kmcoge5ne_defconfig')
| -rw-r--r-- | configs/kmcoge5ne_defconfig | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 088dee63ba0..6740c4c8a97 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -143,3 +143,45 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_ELBC_BR4_OR4=y +CONFIG_BR4_OR4_NAME="BFTIC3" +CONFIG_BR4_OR4_BASE=0xB0000000 +CONFIG_BR4_PORTSIZE_8BIT=y +CONFIG_OR4_AM_256_MBYTES=y +CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR4_CSNT_EARLIER=y +CONFIG_OR4_EAD_EXTRA=y +CONFIG_OR4_SCY_2=y +CONFIG_OR4_TRLX_RELAXED=y |