diff options
| author | Hugh Cole-Baker | 2020-11-22 13:03:45 +0000 |
|---|---|---|
| committer | Kever Yang | 2021-01-21 11:53:25 +0800 |
| commit | acc57ecf05500d2ed47f0d3898245d0029e1cc0c (patch) | |
| tree | b582198697c5235c56b4f1c32646ef12d26636ef /configs/roc-pc-rk3399_defconfig | |
| parent | 83433fdab4920e206700bca33b9040c7978afc9d (diff) | |
rockchip: rk3399-roc-pc: default to SPI bus 1 for SPI-flash
SPI flash on this board is located on bus 1, default to using bus 1 for
SPI flash on both rk3399-roc-pc and -mezzanine, and stop aliasing it to
bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Diffstat (limited to 'configs/roc-pc-rk3399_defconfig')
| -rw-r--r-- | configs/roc-pc-rk3399_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 774707b115b..927b57685d9 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -41,6 +41,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y |