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| author | Wenyou Yang | 2018-02-09 11:34:51 +0800 |
|---|---|---|
| committer | Tom Rini | 2018-03-16 07:30:04 -0400 |
| commit | fed0509c92e0fe29d0ddc9c743719d22c95b7596 (patch) | |
| tree | efe417a3aa1f19076069eb4138e31ffa8731a66b /configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | |
| parent | cb0cb1b0cf20687cf980fbd64c56224f06d566aa (diff) | |
clk: at91: add PLLADIV driver
As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Diffstat (limited to 'configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig')
0 files changed, 0 insertions, 0 deletions