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| author | Swapnil Jakhade | 2022-01-28 13:41:44 +0530 |
|---|---|---|
| committer | Tom Rini | 2022-02-08 11:00:03 -0500 |
| commit | 990ce535ebc3f912769cbc8a651b7eb53545c60d (patch) | |
| tree | 0fe5d9dd4d0bb149f3f6fd30347d4a930b71aaea /configs/zeropi_defconfig | |
| parent | 445c8cf89b7472a6a78854f87de114bc067c1878 (diff) | |
phy: cadence: Sierra: Add PHY PCS common register configurations
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Diffstat (limited to 'configs/zeropi_defconfig')
0 files changed, 0 insertions, 0 deletions