diff options
| author | Tom Rini | 2019-04-29 15:54:04 -0400 |
|---|---|---|
| committer | Tom Rini | 2019-04-29 21:41:40 -0400 |
| commit | d168bcb6fe39108042c0c771f0823a95346a8e7e (patch) | |
| tree | 040ed446b489b31e90e2bfc33f6dfbafe746b31b /configs/zynq_dlc20_rev1_0_defconfig | |
| parent | 6aebc0d11a10f48a54146c5e71bbef15a1a458fc (diff) | |
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'configs/zynq_dlc20_rev1_0_defconfig')
| -rw-r--r-- | configs/zynq_dlc20_rev1_0_defconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index 37c5f3524ae..913581e504b 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -1,11 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_IDENT_STRING=" Xilinx Zynq DLC20 Rev1.0" -CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y |