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authorwdenk2002-11-10 22:06:23 +0000
committerwdenk2002-11-10 22:06:23 +0000
commit7f6c2cbc2bc0721c41bb776242c0b18ec70328e4 (patch)
tree908cb91c8a9d3dec906264120a98fdb06c2ca52a /cpu/arm920t/speed.c
parent2a3cb0207614427d301a4a6f8041267cada14bd8 (diff)
* Vince Husovsky, 7 Nov 2002:
Add "-n" to linker options to get rid of "Not enough room for program headers" problem * Patch by David Müller, 05 Nov 2002 Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ so we can use an already existing name * Patch by Pierre Aubert, 05 Nov 2002 Hardware related improvements in FDC boot code * Patch by Holger Schurig, 5 Nov 2002: Make the PXA really change it's frequency * Patch by Pierre Aubert, 05 Nov 2002 Add support for slave serial Spartan 2 FPGAs * Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet drivers
Diffstat (limited to 'cpu/arm920t/speed.c')
-rw-r--r--cpu/arm920t/speed.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/speed.c
index 1ee0c1a15ae..4942727272d 100644
--- a/cpu/arm920t/speed.c
+++ b/cpu/arm920t/speed.c
@@ -42,7 +42,7 @@
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
- * CONFIG_PLL_INPUT_FREQ should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
@@ -64,7 +64,7 @@ static ulong get_PLLCLK(int pllreg)
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
- return((CONFIG_PLL_INPUT_FREQ * m) / (p << s));
+ return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
}
/* return FCLK frequency */