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| author | Mike Frysinger | 2009-04-04 08:40:13 -0400 |
|---|---|---|
| committer | Mike Frysinger | 2009-04-06 17:37:48 -0400 |
| commit | 8ef929afa43c77c9573caa57c6e17a97a33775c0 (patch) | |
| tree | 06f917337ccae6ecda40a1dc43118bba7f2ca3a4 /cpu/blackfin/cpu.c | |
| parent | c2e07449f546fb375289cdac1a608fdc20357873 (diff) | |
Blackfin: add check for anomaly 05000362
DESCRIPTION:
The column address width settings for banks 2 and 3 are misconnected in
the SDRAM controller. Accesses to bank 2 will result in an error if the
Column Address Width for bank 3 (EB3CAW ) is not set to be the same as
that of bank 2.
WORKAROUND:
If using bank 2, make sure that banks 2 and 3 have the same column address
width settings in the EBIU_SDBCTL register. This must be the case
regardless of whether or not bank 3 is enabled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu/blackfin/cpu.c')
0 files changed, 0 insertions, 0 deletions