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authorMike Frysinger2008-10-11 21:49:06 -0400
committerMike Frysinger2009-01-28 13:26:15 -0500
commitcf8f2efb5f39c5225da92391c14a07eecbeca881 (patch)
tree23b83603277d26634ec68f003a019b1b63e0534c /cpu/blackfin
parentb1e9435b643043dd8fbd1fcc47309c6acb7b3c8e (diff)
Blackfin: handle new anomalies with reset
Workaround fun new anomalies related to software reset of the processor. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu/blackfin')
-rw-r--r--cpu/blackfin/reset.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/cpu/blackfin/reset.c b/cpu/blackfin/reset.c
index d1e34b3f94c..284cea579d0 100644
--- a/cpu/blackfin/reset.c
+++ b/cpu/blackfin/reset.c
@@ -29,26 +29,35 @@ void bfin_reset(void)
*/
__builtin_bfin_ssync();
- while (1) {
+ /* The bootrom checks to see how it was reset and will
+ * automatically perform a software reset for us when
+ * it starts executing after the core reset.
+ */
+ if (ANOMALY_05000353 || ANOMALY_05000386) {
/* Initiate System software reset. */
bfin_write_SWRST(0x7);
/* Due to the way reset is handled in the hardware, we need
- * to delay for 7 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 7. For now,
+ * to delay for 10 SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply 10. For now,
* we'll assume worse case which is a 1:15 ratio.
*/
asm(
"LSETUP (1f, 1f) LC0 = %0\n"
"1: nop;"
:
- : "a" (15 * 7)
+ : "a" (15 * 10)
: "LC0", "LB0", "LT0"
);
/* Clear System software reset */
bfin_write_SWRST(0);
+ /* The BF526 ROM will crash during reset */
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+ bfin_read_SWRST();
+#endif
+
/* Wait for the SWRST write to complete. Cannot rely on SSYNC
* though as the System state is all reset now.
*/
@@ -59,10 +68,11 @@ void bfin_reset(void)
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
+ }
+ while (1)
/* Issue core reset */
asm("raise 1");
- }
}
/* We need to trampoline ourselves up into L1 since our linker