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authorwdenk2003-03-06 21:55:29 +0000
committerwdenk2003-03-06 21:55:29 +0000
commit1cb8e980c41e86760fa93de63f4e4cf643bef9d9 (patch)
treee1993fba07dea51d92f1cec4c814a67173c1f8fb /cpu/mpc8xx
parent500545cc6b83958209128bffa825b3c842a21a4e (diff)
* Patches by David Müller, 31 Jan 2003:
- minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 * Patch by Reinhard Meyer, 5 Feb 2003: fix PLPRCR/SCCR init sequence on 8xx to allow for changes of EBDF by software * Patch by Vladimir Gurevich, 07 Feb 2003: "API-compatibility patch" for 4xx I2C driver
Diffstat (limited to 'cpu/mpc8xx')
-rw-r--r--cpu/mpc8xx/cpu_init.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index abe62094c82..c0ee5de2e9e 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -68,6 +68,14 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
immr->im_sit.sit_piscr = CFG_PISCR;
+ /* System integration timers. Don't change EBDF! (15-27) */
+
+ immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+ reg = immr->im_clkrst.car_sccr;
+ reg &= SCCR_MASK;
+ reg |= CFG_SCCR;
+ immr->im_clkrst.car_sccr = reg;
+
/* PLL (CPU clock) settings (15-30) */
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
@@ -88,14 +96,6 @@ void cpu_init_f (volatile immap_t * immr)
#endif
immr->im_clkrst.car_plprcr = reg;
- /* System integration timers. Don't change EBDF! (15-27) */
-
- immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
- reg = immr->im_clkrst.car_sccr;
- reg &= SCCR_MASK;
- reg |= CFG_SCCR;
- immr->im_clkrst.car_sccr = reg;
-
/*
* Memory Controller:
*/