diff options
| author | Stefan Roese | 2007-03-08 10:13:16 +0100 |
|---|---|---|
| committer | Stefan Roese | 2007-03-08 10:13:16 +0100 |
| commit | 00cdb4ce5e1b42248e7e6522ad0da3421b988afa (patch) | |
| tree | 6fcec3d2d5dbb848b184634579f4afcf0b9c1fd2 /cpu | |
| parent | 2f5df47351910a2936c7741cf111855829200943 (diff) | |
[PATCH] Update AMCC Luan 440SP eval board support
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.
This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/start.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 24b30dfe716..1301cd26d8b 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1361,7 +1361,7 @@ ppcSync: relocate_code: #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. |