* Patch by Gary Jennejohn, 01 Oct 2004:

  - add support for CMC PU2 board
  - add support for I2C on at91rm9200

* Patch by Gary Jennejohn, 28 Sep 2004:
  fix baudrate handling on at91rm9200

4 files changed, 219 insertions, 7 deletions

diff --git a/cpu/at91rm9200/Makefile b/cpu/at91rm9200/Makefile
index dfe50c0b0a0..b7a30c93b20 100644
--- a/cpu/at91rm9200/Makefile
+++ b/cpu/at91rm9200/Makefile
@@ -27,7 +27,7 @@ LIB	= lib$(CPU).a
 
 START	= start.o
 OBJS	= serial.o interrupts.o cpu.o \
-	  at91rm9200_ether.o
+	  at91rm9200_ether.o i2c.o
 
 all:	.depend $(START) $(LIB)
 
diff --git a/cpu/at91rm9200/cpu.c b/cpu/at91rm9200/cpu.c
index c006d9c7e6d..a7e2ca91654 100644
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -35,8 +35,8 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART1
+#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
+#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
 #endif
 
 /* read co-processor 15, register #1 (control register) */
@@ -123,6 +123,9 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_DBGU
    AT91PS_USART us = AT91C_BASE_DBGU;
 #endif
+#ifdef CONFIG_USART0
+   AT91PS_USART us = AT91C_BASE_US0;
+#endif
 #ifdef CONFIG_USART1
    AT91PS_USART us = AT91C_BASE_US1;
 #endif
diff --git a/cpu/at91rm9200/i2c.c b/cpu/at91rm9200/i2c.c
new file mode 100644
index 00000000000..d5d6268dbcb
--- /dev/null
+++ b/cpu/at91rm9200/i2c.c
@@ -0,0 +1,192 @@
+/*
+ *  i2c Support for Atmel's AT91RM9200 Two-Wire Interface
+ *
+ *  (c) Rick Bronson
+ *
+ *  Borrowed heavily from original work by:
+ *  Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
+ *
+ *  Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+*/
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include <at91rm9200_i2c.h>
+
+static int debug = 0;
+
+/*
+ * Poll the i2c status register until the specified bit is set.
+ * Returns 0 if timed out (100 msec)
+ */
+static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
+	int loop_cntr = 10000;
+	do {
+		udelay(100);
+	} while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
+
+	return (loop_cntr > 0);
+}
+
+/*
+ * Generic i2c master transfer entrypoint
+ *
+ * rw == 1 means that this is a read
+ */
+static int
+at91_xfer(unsigned char chip, unsigned int addr, int alen,
+						unsigned char *buffer, int len, int rw)
+{
+	AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
+	int length;
+	unsigned char *buf;
+
+	/* Set the TWI Master Mode Register */
+	twi->TWI_MMR = (chip << 16) | (alen << 8)
+		| ((rw == 1) ? AT91C_TWI_MREAD : 0);
+
+	/* Set TWI Internal Address Register with first messages data field */
+	/* only one address byte is supported  */
+	if (alen > 0)
+		twi->TWI_IADR = addr & 0xff;
+
+	length = len;
+	buf = buffer;
+	if (length && buf) {	/* sanity check */
+		if (rw) {
+			twi->TWI_CR = AT91C_TWI_START;
+			while (length--) {
+				if (!length)
+					twi->TWI_CR = AT91C_TWI_STOP;
+				/* Wait until transfer is finished */
+				if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
+					if (debug)
+						printf("at91_i2c: timeout 1\n");
+					return 1;
+				}
+				*buf++ = twi->TWI_RHR;
+			}
+			if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+				if (debug)
+					printf("at91_i2c: timeout 2\n");
+				return 1;
+			}
+		} else {
+			twi->TWI_CR = AT91C_TWI_START;
+			while (length--) {
+				twi->TWI_THR = *buf++;
+				if (!length)
+					twi->TWI_CR = AT91C_TWI_STOP;
+				if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
+					if (debug)
+						printf("at91_i2c: timeout 3\n");
+					return 1;
+				}
+			}
+			/* Wait until transfer is finished */
+			if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+				if (debug)
+					printf("at91_i2c: timeout 4\n");
+				return 1;
+			}
+		}
+	}
+	return 0;
+}
+
+int
+i2c_probe(unsigned char chip)
+{
+	char buffer[1];
+
+	return at91_xfer(chip, 0, 0, buffer, 1, 1);
+}
+
+int
+i2c_read(unsigned char chip, unsigned int addr, int alen,
+							unsigned char *buffer, int len)
+{
+	/* we only allow one address byte */
+	if (alen > 1)
+		return 1;
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+	/* XXX assume an ATMEL AT24C16 */
+	if (alen == 1) {
+		chip |= (addr >> 8) & 0xff;
+		addr = addr & 0xff;
+	}
+#endif
+	return at91_xfer(chip, addr, alen, buffer, len, 1);
+}
+
+int
+i2c_write(unsigned char chip, unsigned int addr, int alen,
+							unsigned char *buffer, int len)
+{
+	int i;
+	unsigned char *buf;
+
+	/* we only allow one address byte */
+	if (alen > 1)
+		return 1;
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+	/* XXX assume an ATMEL AT24C16 */
+	if (alen == 1) {
+		buf = buffer;
+		/* do single byte writes */
+		for (i = 0; i < len; i++) {
+			chip |= (addr >> 8) & 0xff;
+			addr = addr & 0xff;
+			if (at91_xfer(chip, addr, alen, buf++, 1, 0))
+				return 1;
+		}
+	}
+	return 0;
+#endif
+	return at91_xfer(chip, addr, alen, buffer, len, 0);
+}
+
+/*
+ * Main initialization routine
+ */
+void
+i2c_init(int speed, int slaveaddr)
+{
+	AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
+
+	*AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+	*AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+	*AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_TWI;		/* enable peripheral clock */
+
+	twi->TWI_IDR = 0x3ff;				/* Disable all interrupts */
+	twi->TWI_CR = AT91C_TWI_SWRST;			/* Reset peripheral */
+	twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;	/* Set Master mode */
+
+	/* Here, CKDIV = 1 and CHDIV=CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
+	twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
+
+	printf("Found AT91 i2c\n");
+	return;
+}
+#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/at91rm9200/serial.c b/cpu/at91rm9200/serial.c
index c16c9d4f0ff..fb038510c48 100644
--- a/cpu/at91rm9200/serial.c
+++ b/cpu/at91rm9200/serial.c
@@ -33,14 +33,17 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART1
+#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
+#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
 #endif
 
 /* ggi thunder */
 #ifdef CONFIG_DBGU
 AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
 #endif
+#ifdef CONFIG_USART0
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0;
+#endif
 #ifdef CONFIG_USART1
 AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
 #endif
@@ -50,9 +53,19 @@ void serial_setbrg (void)
 	DECLARE_GLOBAL_DATA_PTR;
 	int baudrate;
 
-	if ((baudrate = gd->bd->bi_baudrate) <= 0)
+	if ((baudrate = gd->baudrate) <= 0)
 		baudrate = CONFIG_BAUDRATE;
-	us->US_BRGR = CFG_AT91C_BRGR_DIVISOR;	/* hardcode so no __divsi3 */
+	if (baudrate == CONFIG_BAUDRATE) {
+		us->US_BRGR = CFG_AT91C_BRGR_DIVISOR;	/* hardcode so no __divsi3 */
+	} else {
+#if 0
+		/* 33 -> 115200 */
+		us->US_BRGR = 33 * (115200/baudrate);
+#else
+		/* MASTER_CLOCK/(16 * baudrate) */
+		us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
+#endif
+	}
 }
 
 int serial_init (void)
@@ -62,6 +75,10 @@ int serial_init (void)
 	*AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;	/* PA 31 & 30 */
 	*AT91C_PMC_PCER = 1 << AT91C_ID_SYS;	/* enable clock */
 #endif
+#ifdef CONFIG_USART0
+	*AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
+	*AT91C_PMC_PCER |= 1 << AT91C_ID_USART0;	/* enable clock */
+#endif
 #ifdef CONFIG_USART1
 	*AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1;
 	*AT91C_PMC_PCER |= 1 << AT91C_ID_USART1;	/* enable clock */